Talk:Hardware emulation

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Questions

This is a very interesting article. There are some aspects that I couldn't understand, though.

The largest fraction of silicon integrated circuit respins are due to [...] functional errors.
- Is respin a defined term in hardware development?
[...] the time required to implement a large design into several FPGAs can be very long and is error-prone.
- I thought hardware can be described in an abstract language, from which both VLSI and FPGA code can be generated automatically. So why should there be a significant time overhead when implementing the FPGA code?
recompiling FPGAs to move probes takes too long.
- Quantitatively, how long does it take to recompile an FPGA to make a significant impact?
- What is a probe and what does it mean to move it?
Simulation acceleration can address the performance shortcomings of simulation to an extent. Here the design is mapped into a hardware accelerator to run much faster and the testbench (and any behavioral design code) continues to run on the simulator on the workstation. A high-bandwidth, low latency channel connects the workstation to the accelerator to exchange signal data between testbench and design.
- What comprises the testbench and what comprises the design? What is separating line between these two terms?
- What's a workstation?
- Why is there a separation between having X run on a hardware accelerator and having Y run on a workstation simulator? Why isn't everything just run on the hardware accelerator?
In some cases, a transaction-level testbench is able to feed as much data to the design being emulated as "live" stimulus.
- What is a transaction-level testbench?
[Accelerators] are not useful for analyzing X-state initialization.
- What is X-state initialization?
[Accelerators] cannot analyze strength resolution [...]
- What is strength resolution?
Photo in article
- What is the Ikos NSIM-64? I couldn't find anything about its manufacturer around the Internet. Can it simulate whatever hardware you would like to have simulated? And how is this simulation actually done in hardware - other than e.g. using FPGAs internally?

Thanks, --Abdull (talk) 17:59, 3 February 2010 (UTC)[reply]