Talk:MIPS instruction set

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Here are some tasks awaiting attention:
  • Cleanup : Number of MIPS architectures. The lead talks about "MIPS architectures", then about "the MIPS architecture".


Influence on SPARC[edit]

I'd like to question the influence on SPARC. There were three RISC designs very early, that were demonstrations of the technology.

  1. The IBM effort under John Cocke. This was virtually unknown outside IBM until much, much later, but may have been the inspiration for IBM projects including ROMP, Power, and PowerPC.
  2. The Berkeley RISC project. An academic project that was probably the main inspiration for SPARC.
  3. The Stanford project. An academic project that was definitely the main inspiration for the commercial MIPS RISC.

SPARC and (commercial) MIPS were developed at much the same time so it is unlikely that commercial MIPS had much influence on SPARC. The original Stanford chip was a bit older than SPARC, and the SPARC people were certainly aware of it, but in looking at the major differences between Stanford and Berkeley RISC (sliding register window only in Berkeley, and not much else) SPARC follows the Berkeley model.

Marice Wilkes states (in the foreword to Patterson/Hennessy) that MIPS is more-or-less the Stanford RISC project while SPARC is the commercialised Berkeley RISC. I therefore reformulated the sentence so that both are credited with influencing later RISCs. --Robbe

Use in TiVo[edit]

I believe the Series II TiVo's use MIPS and that's likely a high enough profile use to warrant a mention.

Free MIPS64 Simulator[edit]

Hello! I belong to a free (as in free speech) MIPS64 CPU Simulator development team. Do you think that it's acceptable to add the simulator's URL to the "External links" sections? The URL is http://www.edumips.org, the simulator's name is EduMIPS64. Thanks!

I think this is a judgement call which depends on whether or not you are able to reference something relevant in the article which is directly relevant to the article topic. 77.101.47.254 (talk) 15:43, 4 July 2013 (UTC)

MIPS licensees: soft IP and hard IP[edit]

A new section similar to ARM_architecture#ARM_licensees would be nice. — Preceding unsigned comment added by Doors5678 (talkcontribs) 13:31, 19 April 2012 (UTC)

Missing JALR instruction?[edit]

Is the "MIPS assembly language" section missing the "jalr" instruction? From the SPIM (MIPS emulator) documentation "Jump and link register - jalr rs, rd - Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31)." — Preceding unsigned comment added by 75.79.68.235 (talk) 21:44, 18 June 2012 (UTC)

CPU family section improvement (table)[edit]

It would be nice to add a column that would detail the instructions width; an another for the supported ABI(s) (application binary interface); and a last one for the supported endianness. Adding a line for the VIPER MIPS32 CPU would be nice to.78.116.90.239 (talk) 17:08, 18 March 2013 (UTC)

move MIPS architecture to MIPS instruction set[edit]

Because it is an instruction set. There is an article covering microarchitectures: List of MIPS microprocessor cores. ScotXW (talk) 11:38, 9 March 2014 (UTC)

The lw and sw instructions are both real and pseudo[edit]

Both lw and sw can be both real instructions or pseudo, depending on the operand. If referring to a 32 bit label address, lw and sw will expand into 2 instructions as below.

   sw          rn, label[31:0]

becomes:

   lui         at, label[31:16]
   sw          rn, label[15:0](at)


   lw          rn, label[31:0]

becomes:

   lui         rn, label[31:16]
   lw          rn, label[15:0](rn)  — Preceding unsigned comment added by 220.233.211.182 (talk) 05:52, 27 May 2014 (UTC) 

Computer architecture courses in universities and technical schools often study the MIPS architecture.[6][edit]

This sentence is in the lead section, but it doesn't get expanded in the main article (courses are only mentioned in the simulator section). The citation does not support the statement; it is just one course listing that happens to use MIPS. I don't dispute the statement, but we should structure it better and support it with secondary sources. --Nczempin (talk) 13:16, 5 December 2014 (UTC)

"Load-store" vs. "register-based"[edit]

The paragraph in question used to say

MIPS is a register based architecture, meaning the CPU uses registers to perform operations on. Other architectures exist, such as stack-based processors and accumulator-based processors.

and now says

MIPS is a load-store architecture, meaning it performs arithmetic and logic operations between CPU registers. Other architectures exist, such as stack-based processors and accumulator-based processors.

If "register-based" is distinguished from "stack-based" and "accumulator-based", into which category do, for example, IBM System/360 and its successors, the PDP-10, the PDP-11, VAX, m68k, and x86 belong? They're not "stack-based", as they don't have an arithmetic stack (code for the PDP-11 and VAX can use auto-increment and auto-decrement addressing modes in a stack-machine fashion, but that's not the only way arithmetic can be done). I wouldn't call them "accumulator-based", as they don't have a single accumulator through which all arithmetic must be done (the PDP-10 documentation called its registers "accumulators", but they're really just general-purpose registers).

However, they're not load-store architectures, as they support memory-to-register arithmetic.

So what do we call those CISC architectures that primarily use registers for arithmetic operations, but support memory-to-register arithmetic and, in some cases, memory-to-memory arithmetic? Guy Harris (talk) 01:15, 10 June 2016 (UTC)

I think they might be called 'memory-register' based; 68k/x86 are definitely not load-store, whilst MIPS is. I changed this as I think load-store is the most specific term here. I guess you're suggesting we should list that term as part of the 'others' ? I didn't yet because I wasn't quite sure what the *exact* accepted term is. I generally just think about 'load-store' and 'everything else' lol.Fmadd (talk) 01:35, 10 June 2016 (UTC)
These days, most of the "everything else" instruction sets are register-memory; the only machines with a single accumulator these days are, I think, some small micro controllers and some virtual machines like the BPF virtual machine, and the only stack machines are the Unisys A series, perhaps some Forth chips, and virtual machines like the JVM (and any chips that implement some or all of the JVM). At least for general-purpose computing, the vast majority of machines that aren't load-store are GPR register-memory machines. Guy Harris (talk) 02:59, 10 June 2016 (UTC)
Ok I fixed it, but I was thinking it might be better to delete this whole paragraph and rely on the reader to click 'RISC' in the intro , and just to be safe add the term 'load/store' there.