|WikiProject Electronics||(Rated Start-class)|
|WikiProject Computing / Hardware||(Rated Start-class)|
According to my Introduction to computer design textbook the Truth table on wikipedia for the NAND gate is incorrect. My textbook claims that the output will only be high if both inputs are low. Wikipedia says that the output will only be low if both inputs are high. could someone please check to make sure which is correct.
- Um.. Check your text book again - this page is correct. A NAND gate is the inversion of an AND gate - AND is 1 when both inputs are 1, NAND is NOT-1 (0) when both inputs are 1. Fresheneesz 08:45, 20 October 2006 (UTC)
Suggested 'Implementation' revision.
I am a Computer Engineering student well versed in logic design. As I was reading this page, I noticed a few semantic inconsistencies in the 'Implementation' section. Following is the original text:
The NAND gate is the easiest to manufacture, and also has the property that any other logic gate can be made from a combination of NAND gates.
My suggested version:
The NAND gate is the easiest to manufacture, and also has the property of functional completeness. That is, any other logic function (AND, OR, etc.) can be implemented using only NAND gates.
My reasoning is that first of all, the inclusion of 'Functional completeness' is a lot more informative, and it promotes further research on the topic. Additionally, the statement "any other logic gate can be made from a combination of NAND gates" is partially false. When you use NAND gates to carry out a function, you are not "making a logic gate". You are instead producing the same output that the other gate would normally produce. A gate is a discreet hardware entity, while a circuit made from a combination of NANDS is not. I would have done this on my own, but being a major change I thought I'd get approval first.
Ghostwo 20:21, 2 February 2007 (UTC)
It has been one week, with no objections. Making the above change. Ghostwo 08:08, 9 February 2007 (UTC)
Isn't the PMOS diagram mistaken?
The NAND gate is only easier to manufacture in DTL and TTL. In the obsolete RTL, it is harder than NOR. In CMOS, it doesn't look any different. Other technologies may differ too. It's just that TTL happened to be the most prevalent technology at the time when digital circuits became common-place.
Is it mistaken?
I noticed the AND gate link in the header was a link to logical conjunction. It seemed more appropriate that it link to the page for AND gates themselves, so I changed it. If it was linked to that page for a reason, feel free to change it back. --188.8.131.52 (talk) 01:17, 19 February 2010 (UTC)