User:Jfishburn/Intentional Clock Skew in Synchronous Circuits
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Intentional clock skew is clock skew that is deliberately designed into a Synchronous circuit to armor it against various kinds of failure, or to enable it to be clocked at a higher rate.
Ideal Clocking with Zero Clock Skew[edit]
What Can Go Wrong[edit]
SETUP Failure[edit]
HOLD Failure[edit]
The Nightmare Scenario: Intermittent HOLD Failure[edit]
For Low-Delay Paths, The Perils of Zero Clock Skew[edit]
A Logic Path with Little Or No Delay Is Close to HOLD Failure[edit]
A Small Amount of Unintentional Skew Causes It To Fail[edit]
Intentional Clock Skew To the Rescue[edit]
Intentional Clock Skew Can Also Speed Up A Circuit[edit]
References[edit]
External links[edit]