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In semiconductor manufacturing, the 2 nm process is the next die shrink after the 3 nm process node. As of 2020, both TSMC and Intel have 2nm products on their roadmaps, with earliest production scheduled for 2023 or later.

Background

In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes;^[1] however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.^[2]

TSMC began research on 2 nm in 2019.^[3] TSMC expected to transition from FinFET to GAAFET transistor types when moving from 3nm to 2nm.^[4] It has been reported that TSMC is expected to enter 2 nm risk production around 2023 or 2024.^[5]

Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027 respectively.^[6] In December 2019, Intel announced plans for 1.4 nm production in 2029.^[7]

In August 2020, TSMC began building a R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021.^[8] In September 2020 (SEMICOM Taiwan 2020) it was reported that TSMC Chairman Mark Liu had stated the company would build a plant for the 2 nm node at Hsinchu in Taiwan, and that it could also install production at Taichung dependent on demand.^[9]

At the end of 2020, seventeen of the European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm as well as a designing and manufacturing custom processors, assigning up to 145 billion Euro in funds.^[10]^[11]

In May of 2021, IBM announced it had produced 2 nm class transistor using three silicon layer nanosheets with a gate length of 12nm.^[12]^[13] (12nm gate length is the dimension defined by the ITRS to be associated with the "2nm" process node)^[14]

References

^ Patterson, Alan (12 Sep 2018), "TSMC: Chip Scaling Could Accelerate", www.eetimes.com
^ Merritt, Rick (4 March 2019), "SPIE Conference Predicts Bumpy Chip Roadmap", www.eetasia.com
^ Zafar, Ramish (12 June 2019), TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report
^ "Highlights of the day: TSMC reportedly adopts GAA transistors for 2nm chips", www.digitimes.com, 21 Sep 2020
^ "TSMC has achieved a breakthrough in 2nm, will adopt GAA technology and put it into production in 2023-2024", finance.technews.tw, 13 July 2020
^ Cutress, Ian, "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm", www.anandtech.com
^ Cutress, Dr Ian. "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm". www.anandtech.com.
^ Wang, Lisa (26 Aug 2020), "TSMC developing 2nm tech at new R&D center", taipeitimes.com
^ Chien-Chung, Chang; Huang, Frances (23 Sep 2020), "TSMC to build 2nm wafer plant in Hsinchu", focustaiwan.tw
^ Dahad, Nitin (9 Dec 2020), "EU Signs €145bn Declaration to Develop Next Gen Processors and 2nm Technology", www.eetimes.eu
^ Joint declaration on processors and semiconductor technologies, EU, 7 Dec 2020
^ Nellis (6 May 2021), "IBM unveils 2-nanometer chip technology for faster computing", Reuters, retrieved 2021-05-06 {{citation}}: Unknown parameter |f irst= ignored (help)
^ Johnson, Dexter (6 May 2021), "IBM Introduces the World's First 2-nm Node Chip", IEEE Spectrum
^ INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - EXECUTIVE SUMMARY (PDF), ITRS, 2017, Table ES2, p.18

@@ Line 10: / Line 10: @@
 [[Intel]]'s 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027 respectively.<ref>{{Citation| url = https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029| title = Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm| first=  Ian| last= Cutress| work =www.anandtech.com}}</ref> In December 2019, Intel announced plans for 1.4&nbsp;nm production in 2029.<ref name="auto">{{Cite web|url=https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029|title=Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm|first=Dr Ian|last=Cutress|website=www.anandtech.com}}</ref>
-In August 2020, TSMC began building a R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021.<ref>{{citation| url  =https://taipeitimes.com/News/front/archives/2020/08/26/2003742295 | title = TSMC developing 2nm tech at new R&D center | first = Lisa | last = Wang | date = 26 Aug 2020 | work = taipeitimes.com }}</ref> In September 2020 (SEMICOM Taiwan 2020) it was reported that TSMC Chairman Mark Liu had stated the company would build a plant for the 2 nm node at [[Hsinchu]] in [[Taiwan]], and that it could also install production at [[Taichung]] dependent on demand.<ref>{{citation| url  =https://focustaiwan.tw/sci-tech/202009230017 | title = TSMC to build 2nm wafer plant in Hsinchu
+In August 2020, TSMC began building a R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021.<ref>{{citation| url  =https://taipeitimes.com/News/front/archives/2020/08/26/2003742295 | title = TSMC developing 2nm tech at new R&D center | first = Lisa | last = Wang | date = 26 Aug 2020 | work = taipeitimes.com }}</ref> In September 2020 (SEMICOM Taiwan 2020) it was reported that TSMC Chairman Mark Liu had stated the company would build a plant for the 2 nm node at [[Hsinchu]] in [[Taiwan]], and that it could also install production at [[Taichung]] dependent on demand.<ref>{{citation| url  =https://focustaiwan.tw/sci-tech/202009230017 | title = TSMC to build 2nm wafer plant in Hsinchu  | first1   =Chang | last1 = Chien-Chung | first2 =  Frances | last2 = Huang | date = 23 Sep 2020 | work = focustaiwan.tw }}</ref>
- | first1   =Chang | last1 = Chien-Chung | first2 =  Frances | last2 = Huang | date = 23 Sep 2020 | work = focustaiwan.tw }}</ref>
 At the end of 2020, seventeen of the [[European Union]] countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm as well as a designing and manufacturing custom processors, assigning up to 145 billion Euro in funds.<ref>{{citation |url  =https://www.eetimes.eu/eu-signs-e145bn-declaration-to-develop-next-gen-processors-and-2nm-technology/ | title = EU Signs €145bn Declaration to Develop Next Gen Processors and 2nm Technology | first=Nitin | last = Dahad | date = 9 Dec 2020 | work = www.eetimes.eu}}</ref><ref>{{citation| url= https://ec.europa.eu/digital-single-market/en/news/joint-declaration-processors-and-semiconductor-technologies | title = Joint declaration on processors and semiconductor technologies |publisher = EU | date = 7 Dec 2020 }}</ref>
-In May of 2021, [[IBM]] announced it had produced 2 nm chipmaking technology.<ref>{{Cite news|last=Nellis|first=Stephen|date=2021-05-06|title=IBM unveils 2-nanometer chip technology for faster computing|language=en|work=Reuters|url=https://www.reuters.com/article/us-ibm-semiconductors-idUSKBN2CN12S|access-date=2021-05-06}}</ref>  IBM "maintains a chip manufacturing research center in Albany, New York that produces test runs of chips and has joint technology development deals with Samsung and Intel Corp to use IBM’s chipmaking technology".
+In May of 2021, [[IBM]] announced it had produced 2 nm class transistor using three silicon layer nanosheets with a gate length of 12nm.<ref>{{Citation| last=Nellis|f irst=Stephen| date=6 May 2021| title=IBM unveils 2-nanometer chip technology for faster computing| language=en| work=Reuters| url=https://www.reuters.com/article/us-ibm-semiconductors-idUSKBN2CN12S| access-date=2021-05-06}}</ref><ref>{{citation| url = https://spectrum.ieee.org/nanoclast/semiconductors/nanotechnology/ibm-introduces-the-worlds-first-2nm-node-chip | title = IBM Introduces the World’s First 2-nm Node Chip |first = Dexter | last = Johnson | date = 6 May 2021 | work = IEEE Spectrum }}</ref> (12nm gate length is the dimension defined by the [[International Technology Roadmap for Semiconductors|ITRS]] to be associated with the "2nm" process node)<ref>{{citation| url = https://irds.ieee.org/images/files/pdf/2017/2017IRDS_ES.pdf | at = Table ES2, p.18 | title = INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - EXECUTIVE SUMMARY | publisher = ITRS | year = 2017 }}</ref>
 ==References==

Semiconductor device fabrication

MOSFET scaling (process nodes)
020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977 1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2024
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
v t e

Revision as of 09:29, 7 May 2021

Background

References

Further reading