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{{Power Architecture}}
{{Power Architecture}}
'''POWER9''' is a family of [[superscalar]], [[Multithreading_(computer_architecture)|Multithreading]], [[symmetric multiprocessor]]s based on the [[Power Architecture]] announced in August 2016 at the [[Hot Chips]] conference.<ref name="pcworld-hotchips"/>
'''POWER9''' is a family of [[superscalar]], [[Multithreading_(computer_architecture)|Multithreading]], [[symmetric multiprocessor]]s based on the [[Power Architecture]] announced in August 2016 at the [[Hot Chips]] conference.<ref name="pcworld-hotchips"/>
The POWER9 based processors will be manufactured using a [[14 nm]] [[FinFET]] process,<ref name="mccredie-openpowersummit" /> in 12- and 24-core versions, for [[Scalability#Horizontal and vertical scaling|scale out]] and [[Scalability#Horizontal and vertical scaling|scale up]] applications,<ref name="mccredie-openpowersummit" /> and possibly other variations, since the POWER9 architecture is open for licensing and modification by the [[OpenPOWER Foundation]] members.<ref>{{cite web|last1=Williams|first1=Chris|title=Power9: Google gives Intel a chip-flip migraine, IBM tries to lures big biz|url=https://www.theregister.co.uk/2016/04/07/open_power_summit_power9/|publisher=The Register|language=en|date=2016-04-07}}</ref>
The POWER9 based processors are being manufactured using a [[14 nm]] [[FinFET]] process,<ref name="mccredie-openpowersummit" /> in 12- and 24-core versions, for [[Scalability#Horizontal and vertical scaling|scale out]] and [[Scalability#Horizontal and vertical scaling|scale up]] applications,<ref name="mccredie-openpowersummit" /> and possibly other variations, since the POWER9 architecture is open for licensing and modification by the [[OpenPOWER Foundation]] members.<ref>{{cite web|last1=Williams|first1=Chris|title=Power9: Google gives Intel a chip-flip migraine, IBM tries to lures big biz|url=https://www.theregister.co.uk/2016/04/07/open_power_summit_power9/|publisher=The Register|language=en|date=2016-04-07}}</ref>


== Design ==
== Design ==

Revision as of 23:34, 5 April 2018

POWER9
General information
Launched2017
Designed byIBM
Common manufacturer
Performance
Max. CPU clock rate4 GHz[1]
Cache
L1 cache32+32 KB per core[1]
L2 cache512 KB per core[1]
L3 cache120 MB per chip[1]
L4 cachevia Centaur[1]
Architecture and classification
Technology node14 nm (FinFET)
Instruction setPower Architecture (Power ISA v.3.0)
Physical specifications
Cores
  • 12 SMT8 cores or 24 SMT4 cores on die[2][3][4]
History
PredecessorPOWER8
SuccessorPOWER10
POWER, PowerPC, and Power ISA architectures
NXP (formerly Freescale and Motorola)
IBM
IBM/Nintendo
Other
Related links
Cancelled in gray, historic in italic

POWER9 is a family of superscalar, Multithreading, symmetric multiprocessors based on the Power Architecture announced in August 2016 at the Hot Chips conference.[2] The POWER9 based processors are being manufactured using a 14 nm FinFET process,[3] in 12- and 24-core versions, for scale out and scale up applications,[3] and possibly other variations, since the POWER9 architecture is open for licensing and modification by the OpenPOWER Foundation members.[5]

Design

Scale Out / Scale Up

  • IBM POWER9 SO – scale-out variant, optimized for dual socket computers with up to 120 GB/s bandwidth to directly attached DDR4 memory[1][3][6] (targeted for release in 2017)
  • IBM POWER9 SU – scale-up variant, optimized for four sockets or more, for large NUMA machines with up to 230 GB/s bandwidth to buffered memory[1][6]

Both POWER9 variants can ship in versions with some cores disabled due to yield reasons, as such Raptor Computing Systems first sold 4-core chips, and even IBM initially sold its AC922 systems with no more than 22-core chips, even both types of chips have 24 cores on their dies.[7][4]

Core

The POWER9 core comes in two variants, one is four-way multithreading called SMT4 and one eight-way called SMT8.[1] The SMT4- and SMT8-cores are quite similar, in that they consist of a number of so-called slices fed by common schedulers. A slice is a rudimentary 64-bit single threaded processing core with load store unit (LSU), integer unit (ALU) and a vector scalar unit (VSU, doing SIMD and floating point). A super-slice is the combination of two slices. An SMT4-core consists of a 32 KB L1 cache, a 32 KB L1 data cache, an instruction fetch unit (IFU) and an instruction sequencing unit (ISU) which feeds two super-slices. An SMT8-core has two sets of L1 caches and, IFUs and ISUs to feed four super-slices. The result is that the 12-core and 24-core versions of POWER9 each consist of the same amount of slices, i.e. 96 each and the same amount of L1 cache.

A POWER9 core, whether SMT4 and SMT8, has a 12-stage pipeline (five stages shorter than its predecessor, the POWER8) but aims to retain the clock frequency of around 4 GHz.[1] It will be the first to incorporate elements of the Power ISA v.3.0 that was released in December 2015, including the VSX-3 instructions[8] The POWER9 design is made to be modular and used in more processor variants and used for licensing, on a different fabrication process than IBM's.[6] On chip are co-processors for compression and cryptography, as well as a large low-latency eDRAM L3 cache.[3]

I/O

A lot of facilities are on-chip for helping with massive off-chip I/O performance:

  • The SO variant has integrated DDR4 controllers for directly attached RAM, while the SU variant will use the off-chip Centaur architecture introduced with POWER8 to include high performance eDRAM L4 cache and memory controllers for DDR4 RAM.[1][3]
  • The Bluelink interconnects for close attachment of graphics co-processors from Nvidia (over NVLink v.2) and OpenCAPI accelerators.[9]
  • General purpose PCIe v.4 connections for attaching regular ASICs, FPGAs and other peripherals as well as CAPI 2.0 and CAPI 1.0 devices designed for POWER8.
  • Multiprocessor (symmetric multiprocessor system) links to connect other POWER9 processors in on the same motherboard, or in other closely attached enclosures.

Chip Types

POWER9 chips can be made with two types of cores, and in a Scale Out or Scale Up configuration. POWER9 cores are either SMT4 or SMT8, with SMT8 cores intended for PowerVM systems, while the SMT4 cores are intended for PowerNV systems, which do not use PowerVM, and predominantly run Linux. With POWER9, chips made for Scale Out can support directly-attached memory, while Scale Up chips are intended for use with machines with more than two CPU sockets, and use buffered memory.[10][1]

POWER9 Chips
PowerNV PowerVM
24 × SMT4 Core 12 × SMT8 Core
Scale Out Nimbus unknown
Scale Up Cumulus

Modules

The IBM Portal for OpenPOWER lists the three available modules of the Nimbus chip:

  • Sforza — 50 mm × 50 mm, 4 DDR4, 48 PCIe Lanes, 1 XBus 4B[11]
  • Monza — 68.5 mm × 68.5 mm, 8 DDR4, 34 PCIe Lanes, 1 XBus 4B, 48 OpenCAPI lanes[12]
  • LaGrange — 68.5 mm × 68.5 mm, 8 DDR4, 42 PCIe Lanes, 2 XBus 4B, 16 OpenCAPI lanes[13]

Sforza modules use a Land grid array 2601-pin socket.[14]

Systems

Raptor Computing Systems / Raptor Engineering

Talos II — two-socket workstation and development platform using Sforza processors;[15] available as 4U server, tower, or EATX mainboard. Marketed as secure and owner-controllable with free and open-source software and firmware. Initially shipping with 4-core[16], 8-core[17], and 18-core[18] chip options until greater core chips are available.[19][20]

Google/Rackspace partnership

Barreleye G2 / Zaius — two-socket server platform using LaGrange processors;[15] both the Barreleye G2 and Zaius chassis use the Zaius POWER9 motherboard[21][22][23]

IBM

Power Systems AC922 — 2U, 2× POWER9 Monza, SMT4 cores, with up to 6× Nvidia Volta GPUs, 2× CAPI 2.0 attached accelerators and 1 TB DDR4 RAM. AC here is an abbreviation for Accelerated Computing; this system is also known as "Witherspoon" or "Newell".[15][24][25][26][27]

Power Systems L922 — 2U, 1-2× POWER9, 8-12 SMT8 cores per processor, up to 4 TB DDR4 RAM, PowerVM running Linux.[28][29]

Power Systems S914 — 4U, 1× POWER9, 4-8 SMT8 cores, up to 1 TB DDR4 RAM, PowerVM running AIX/IBM i/Linux.[28][29]

Power Systems S922 — 2U, 1-2× POWER9, 4-10 SMT8 cores per processor, up to 4 TB DDR4 RAM, PowerVM running AIX/IBM i/Linux.[28][29]

Power Systems S924 — 4U, 2× POWER9, 8-12 SMT8 cores per processor, up to 4 TB DDR4 RAM, PowerVM running AIX/IBM i/Linux.[28][29][30]

Power Systems H922 — 2U, 1-2× POWER9, 4-10 SMT8 cores per processor, up to 4 TB DDR4 RAM, PowerVM running SAP HANA (on Linux) with AIX/IBM i on up to 25% of the system.[28][29][31]

Power Systems H924 — 4U, 2× POWER9, 8-12 SMT8 cores per processor, up to 4 TB DDR4 RAM, PowerVM running SAP HANA (on Linux) with AIX/IBM i on up to 25% of the system.[28][29][31]

Penguin Computing

Magna PE2112GTX — two-socket, 2U server for high performance computing using LaGrange processors. Manufactured by Wistron.[32]

Supercomputers

IBM

Summit and Sierra — The United States Department of Energy together with Oak Ridge National Laboratory and Lawrence Livermore National Laboratory have contracted IBM and Nvidia to build two supercomputers, the Summit and the Sierra, that will be based on POWER9 processors coupled with Nvidia's Volta GPUs. These systems are slated to go online in 2017.[33][34][35] Sierra will be based on IBM's Power Systems AC922 compute node.[25] The first racks of Summit were delivered to Oak Ridge National Laboratory on 31 July 2017.[36]

MareNostrum 4 — One of the three clusters in the emerging technologies block of the fourth MareNostrum supercomputer is a POWER9 cluster with Nvidia Volta GPUs. This cluster is expected to provide more than 1.5 petaflops of computing capacity when installed. The emerging technologies block of the MareNostrum 4 exists to test if new developments might be "suitable for future versions of MareNostrum".[37]

Operating system support

As with its predecessor, POWER9 is supported by IBM AIX, IBM i, and Linux (both running with and without PowerVM).

Implementation of POWER9 support in the Linux kernel began with version 4.6 in March 2016.[38]

RHEL, SUSE, and Debian GNU/Linux are supported as of November 2017.[39][40][41]

See also

References

  1. ^ a b c d e f g h i j k Big Blue Aims For The Sky With Power9
  2. ^ a b Shah, Agam (2016-08-23). "IBM's 24-core Power9 chip: 5 things you need to know". PCWorld.
  3. ^ a b c d e f McCredie, Brad (April 2016). "OpenPOWER and the Roadmap Ahead" (presentation). OpenPOWER Foundation.
  4. ^ a b Morgan, Timothy Prickett (2017-12-05). "Power9 To The People". The Next Platform. the Nimbus Power9 chip used in the AC922 is a single chip module that has 24 cores on the die. The Summit and Sierra machines based on the AC922 are getting 22 core versions of the chips ... IBM could later, as Power9 yields improve, add a 24 core option.
  5. ^ Williams, Chris (2016-04-07). "Power9: Google gives Intel a chip-flip migraine, IBM tries to lures big biz". The Register.
  6. ^ a b c The Prospects For A Power9 Revolution
  7. ^ 2017, (c) Raptor Engineering, LLC 2009 -. "Raptor Computing Systems::CP9M01 Intro". www.raptorcs.com. Retrieved 2017-11-17. {{cite web}}: |last= has numeric name (help)CS1 maint: multiple names: authors list (link) CS1 maint: numeric names: authors list (link)
  8. ^ Add full Power ISA 3.0 / POWER9 binutils support
  9. ^ Nvidia's NVLink 2.0 will first appear in Power9 servers next year
  10. ^ Stuecheli, Jeff (26 January 2017). "Webinar POWER9" (Video recording / slides). AIX Virtual User Group. - Slides (PDF) - AIX VUG page has links to slides and video
  11. ^ IBM Portal for OpenPOWER - POWER9 - Sforza Module
  12. ^ IBM Portal for OpenPOWER - POWER9 - Monza Module
  13. ^ IBM Portal for OpenPOWER - POWER9 - LaGrange Module
  14. ^ "T2P9D01 Mainboard User's Guide" (pdf). Raptor Computing Systems. 2018.
  15. ^ a b c Raptor Computing Systems Wiki - OpenPOWER
  16. ^ 2018, (c) Raptor Engineering, LLC 2009 -. "Raptor Computing Systems::CP9M01". www.raptorcs.com. Retrieved 2018-03-03. {{cite web}}: |last= has numeric name (help)CS1 maint: multiple names: authors list (link) CS1 maint: numeric names: authors list (link)
  17. ^ 2018, (c) Raptor Engineering, LLC 2009 -. "Raptor Computing Systems::CP9M02". www.raptorcs.com. Retrieved 2018-03-03. {{cite web}}: |last= has numeric name (help)CS1 maint: multiple names: authors list (link) CS1 maint: numeric names: authors list (link)
  18. ^ 2018, (c) Raptor Engineering, LLC 2009 -. "Raptor Computing Systems::CP9M06". www.raptorcs.com. Retrieved 2018-03-03. {{cite web}}: |last= has numeric name (help)CS1 maint: multiple names: authors list (link) CS1 maint: numeric names: authors list (link)
  19. ^ "Raptor Computing Systems::TL2WK2" (product description). Raptor Computing Systems.
  20. ^ 2017, (c) Raptor Engineering, LLC 2009 -. "Raptor Computing Systems::Frequently Asked Questions". www.raptorcs.com. Retrieved 2017-11-17. {{cite web}}: |last= has numeric name (help)CS1 maint: multiple names: authors list (link) CS1 maint: numeric names: authors list (link)
  21. ^ Zipfel, John; Lippert, Rob. "Introducing Zaius, Google and Rackspace's open server running IBM POWER9" (blog post). Google Cloud Platform Blog. Google.
  22. ^ Lippert, Rob; Sullivan, Aaron; Gangidi, Adi; Yeh, Poly (2016-12-07). "Zaius / Barreleye G2 Specification Chassis, Motherboard, Lunchbox Power Supply - Revision 0.5.3" (pdf). Github. Open Compute Project.
  23. ^ Sullivan, Aaron (2017-03-08). "The Latest on Our Zaius /Barreleye G2 Open Compute-OpenPOWER Server" (blog post). The Official Rackspace Blog. Rackspace.
  24. ^ David Bader - Twitter
  25. ^ a b How you can Boost Acceleration with OpenCAPI, Today!
  26. ^ IBM Power System AC922 (8335-GTG) server helps you to harness breakthrough accelerated AI, HPDA, and HPC performance for faster time to insight
  27. ^ "IBM Power System AC922 - Details - United States". IBM Marketplace. 6 December 2017.
  28. ^ a b c d e f https://www.theregister.co.uk/2018/02/14/ibm_power9_servers/ Big Blue levels up server sextet with POWER9 for IBM i, AIX, HANA, Linux
  29. ^ a b c d e f https://www.nextplatform.com/2018/02/15/ins-outs-ibms-power9-zz-systems/ The Ins And Outs Of IBM’s Power9 ZZ Systems
  30. ^ Griffiths, Nigel (14 February 2018). "IBM POWER9 Scale-Out S924 First Look" (video). YouTube.
  31. ^ a b Morgan, Timothy Prickett (14 February 2018). "At Long Last, IBM i Finally Gets Power9 - IT Jungle". IT Jungle.
  32. ^ Hill, Thomas (2017-11-15). "@PenguinHPC showing off the results of true open collaboration with their latest #POWER9 system #openpower #hpc #SC17pic.twitter.com/HdEHQ0vwNi". Twitter. Retrieved 16 November 2017.
  33. ^ NVIDIA Volta, IBM POWER9 Land Contracts For New US Government Supercomputers
  34. ^ ORNL Summit home page
  35. ^ Lawrence Livermore signs contract with IBM
  36. ^ ORNL building world’s smartest supercomputer
  37. ^ "MareNostrum". BSC-CNS. Barcelona Supercomputing Center. Retrieved 30 October 2017.
  38. ^ "Linux 4.6 Begins Laying The Foundation For POWER9". Phoronix. March 18, 2016.
  39. ^ "Red Hat Enterprise Linux 7.4 for IBM Power LE (POWER9) - Release Notes - Red Hat Customer Portal". access.redhat.com. Retrieved 2017-11-17.
  40. ^ "PPC64 - Debian Wiki". wiki.debian.org. Retrieved 2017-11-17.
  41. ^ "SUSE Linux Enterprise Server for POWER | SUSE". www.suse.com. Retrieved 2017-11-17.
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