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Flip chip

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This article is about the semiconductor mounting technique. For the DEC PDP module, see Flip Chip (PDP module). For the CPU format, see Flip-chip pin grid array.
Intel Mobile Celeron in a flip-chip BGA package (FCBGA-479); the silicon die appears dark blue
Underside of a die from a flip chip package

Flip chip, also known as controlled collapse chip connection or its abbreviation, C4,[1] is a method for interconnecting semiconductor devices, such as IC chips and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Dept., Utica, N.Y.[2] The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and wires are used to interconnect the chip pads to external circuitry.[3]

Process steps

  1. Integrated circuits are created on the wafer.
  2. Pads are metallized on the surface of the chips.
  3. A solder ball is deposited on each of the pads, in a process called wafer bumping
  4. Chips are cut.
  5. Chips are flipped and positioned so that the solder balls are facing the connectors on the external circuitry.
  6. Solder balls are then remelted (typically using hot air reflow).
  7. Mounted chip is “underfilled” using a (capillary, shown here) electrically-insulating adhesive.[4][5][6][7]

Comparison of mounting technologies

Wire bonding/thermosonic bonding

The interconnections in a power package are made using thick aluminium wires (250 to 400 µm) wedge-bonded

In typical semiconductor fabrication systems chips are built up in large numbers on a single large wafer of semiconductor material, typically silicon. The individual chips are patterned with small pads of metal near their edges that serve as the connections to an eventual mechanical carrier. The chips are then cut out of the wafer and attached to their carriers, typically via wire bonding such as thermosonic bonding. These wires eventually lead to pins on the outside of the carriers, which are attached to the rest of the circuitry making up the electronic system.

Flip chip

Side-view schematic of a typical flip chip mounting

Processing a flip chip is similar to conventional IC fabrication, with a few additional steps.[8] Near the end of the manufacturing process, the attachment pads are metalized to make them more receptive to solder. This typically consists of several treatments. A small dot of solder is then deposited on each metalized pad. The chips are then cut out of the wafer as normal.

To attach the flip chip into a circuit, the chip is inverted to bring the solder dots down onto connectors on the underlying electronics or circuit board. The solder is then re-melted to produce an electrical connection, typically using a thermosonic bonding or alternatively reflow solder process.[9]

This also leaves a small space between the chip's circuitry and the underlying mounting. In many cases an electrically-insulating adhesive is then "underfilled" to provide a stronger mechanical connection, provide a heat bridge, and to ensure the solder joints are not stressed due to differential heating of the chip and the rest of the system. The underfill distributes the thermal expansion mismatch between the chip and the board, preventing stress concentration in the solder joints which would lead to premature failure.[10]

In 2008, High-speed mounting methods evolved through a cooperation between Reel Service Ltd. and Siemens AG in the development of a high speed mounting tape known as 'MicroTape'[1]. By adding a tape-and-reel process into the assembly methodology, placement at high speed is possible, achieving a 99.90% pick rate and a placement rate of 21,000 cph (components per hour), using standard PCB assembly equipment.

Advantages

The resulting completed flip chip assembly is much smaller than a traditional carrier-based system; the chip sits directly on the circuit board, and is much smaller than the carrier both in area and height. The short wires greatly reduce inductance, allowing higher-speed signals, and also conduct heat better.

Disadvantages

Flip chips have several disadvantages.

The lack of a carrier means they are not suitable for easy replacement, or unaided manual installation. They also require very flat mounting surfaces, which is not always easy to arrange, or sometimes difficult to maintain as the boards heat and cool. This limits the maximum device size.

Also, the short connections are very stiff, so the thermal expansion of the chip must be matched to the supporting board or the connections can crack.[11] The underfill material acts as an intermediate between the difference in CTE of the chip and board.

History

The process was originally introduced commercially by IBM in the 1960s for individual transistors and diodes packaged for use in their mainframe systems.[12]

Alternatives

Since the flip chip's introduction a number of alternatives to the solder bumps have been introduced, including gold balls or molded studs, electrically conductive polymer and the "plated bump" process that removes an insulating plating by chemical means. Flip chips have recently gained popularity among manufacturers of cell phones and other small electronics where the size savings are valuable.[citation needed]

See also

References

  1. ^ E. J. Rymaszewski, J. L. Walsh, and G. W. Leehan, "Semiconductor Logic Technology in IBM" IBM Journal of Research and Development, 25, no. 5 (September 1981): 605.
  2. ^ Filter Center, Aviation Week & Space Technology, September 23, 1963, v. 79, no. 13, p. 96.
  3. ^ Peter Elenius and Lee Levine, Chip Scale Review. “Comparing Flip-Chip and Wire-Bond Interconnection Technologies.” July/August 2000. Retrieved July 30, 2015.
  4. ^ "BGA Underfill for COTS Ruggedization". NASA. 2019.
  5. ^ "Underfill revisited: How a decades-old technique enables smaller, more durable PCBs". 2011.
  6. ^ "Underfill".
  7. ^ "Underfill Applications, Materials & Methods". 2019.
  8. ^ George Riley, Flipchips.com. “Solder Bump Flip Chip.” November 2000. Retrieved July 30, 2015.
  9. ^ https://www.analog.com/media/en/technical-documentation/application-notes/AN-617.pdf
  10. ^ Venkat Nandivada. "Enhance Electronic Performance with Epoxy Compounds". Design World. 2013.
  11. ^ Demerjian, Charlie (2008-12-17), Nvidia chips show underfill problems, The Inquirer, retrieved 2009-01-30
  12. ^ George Riley, Introduction to Flip Chip: What, Why, How, Flipchips.com October 2000.
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