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Flat Panel Display Link, more commonly referred to as FPD-Link, is the original high-speed digital video interface created in 1996 by National Semiconductor (now within Texas Instruments). It is a free and open standard for connecting the output from a graphics processing unit in a laptop, tablet computer, flat panel display, or LCD television to the display panel's timing controller. Most laptops, tablet computers, flat-panel monitors, and TVs use the interface internally.
FPD-Link and LVDS
FPD-Link was the first large-scale application of the low-voltage differential signaling (LVDS) standard. National Semiconductor immediately provided interoperability specifications for the FPD-Link technology in order to promote it as a free and open standard, and thus other IC suppliers were able to copy it. FlatLink by TI was the first interoperable version of FPD-Link.
By the end of the twentieth century, the major notebook computer manufacturers created the Standard Panels Working Group (SPWG) and made FPD-Link / FlatLink the standard for transferring graphics and video through the notebook's hinge.
Transferring the RGB video-interface
FPD-Link became successful at transmitting 18-bit RGB raw video because it reduced the cable size and improved the electromagnetic compatibility by using LVDS. It uses LVDS to transmit the video data on three twisted pair, and another pair to transmit the LVDS clock signal. These four differential pairs are carrying the same information previously transferred over 22 wires, which is almost a 65% wire reduction. In addition, the close coupling of the twisted pair wires improves the EMC because the equal and opposite LVDS currents in the wires create equal and opposite electromagnetic fields that tend to cancel each other's effects. This reduces the radiated emissions. The reduced vulnerability to electrical noise interference comes from the fact the noise affects both signals commonly. Since the LVDS receiver senses the difference between the two commonly affected signals, it senses no impact from the common mode noise.
The FPD-Link data transmission scheme serializes seven single-ended data bits per clock cycle into each of the LVDS channels. Therefore, the LVDS bit rate is 7 times the frequency of the clock signal. For example, in the 18-bit RGB application, there are 6 bits each for R, G, and B and an additional 3 bits for horizontal and vertical sync and an enable signal. This means there are 21 total data signals in each clock cycle, which means the 7 to 1 serialization reduces this down to 3 data channels. Then if the clock signal is 50 MHz the LVDS streaming video data rate will be 350 Mbit/s per channel, and the total data transfer rate will be 1,050 Mbit/s over the 3 channels.
This same scheme scales to 24-bit and 30-bit color in the following manner. An FPD-Link interface with 4 data channels and 1 clock (4D+C) then reduces the 28-bit input down to 4 pairs plus the clock, which is perfect for 8-bits per RGB plus 4 video control bits. A 5D+C FPD-Link interface serializes 35-bits per clock cycle, which is 10-bits per RGB plus 5 video control bits.
Automotive and more applications
The automotive environment is known to be one of the harshest for electronic equipment due to inherent extreme temperatures and electrical transients. In order to satisfy these stringent reliability requirements, the FPD-Link II and III chipsets meet or exceed the AEC-Q100 automotive reliability standard for integrated circuits, and the ISO 10605 standard for automotive ESD applications.
Another display interface based on FPD-Link is OpenLDI. It enables longer cable lengths because of a built-in DC balance coding to reduce the effects of intersymbol interference. In the OpenLDI version of DC balance coding, one of the seven serialized bits indicates whether the coding scheme needs to invert the other six bits transmitted in the clock period to maintain DC balance. Therefore, each LVDS pair other than the clock pair effectively transmits six bits per clock cycle. However, OpenLDI lost the video-transfer standards competition to Digital Visual Interface (DVI) in the early twenty-first century, and the result was stand-alone LCD panels using DVI to receive video from a desktop computer.
FPD-Link II was introduced in 2006 and is an improved version of FPD-Link. National Semiconductor designed it specifically for automotive infotainment and camera interface applications. FPD-Link II embeds the clock in the data signal and therefore uses only one differential pair to transmit both the clock and video data. This further reduces the size, weight, and cost of cables for infotainment and safety camera applications. For example, the 24-bit color application now uses only one twisted pair instead of the 5 twisted pair used by FPD-Link.
There are additional benefits from FPD-Link II. For example, the car makers appreciate the increased cable length even with reduced cable cost. This is because of the embedded clock feature that eliminates the timing skew between clock and data signals. This was the limiting factor to cables with separate clock and data pairs because all pairs had to be manufactured at precisely equal length to control the timing skew between the clock and data pairs. This length matching added to the cable cost.
Another benefit for FPD-Link II comes from adding DC balance to the signals. Because the signal is DC balanced the application can use AC coupling, which eliminates the ground current problem between data source and destination. This is critical in the automotive applications because of the potential for large transient currents that can damage sensitive electronic equipment.
The higher resolution applications required FPD-Link II to increase the data throughput. It started at about 1 Gbit/s data throughput on a single twisted pair which is well within the capability for LVDS technology. But for the applications that required up to 1.8 Gbit/s over a single pair, LVDS was not as reliable as necessary for the automotive applications. By changing from LVDS to current mode logic (CML), the newest FPD-Link II chipsets were able to reliably send high bit-rate video streams over cables longer than 10 m.
FPD-Link III was introduced in 2010. Further improving FPD-Link II, FPD-Link III's major feature is embedding a bidirectional communication channel on the same differential pair. This bidirectional channel transfers control signals between source and destination in addition to the clock and streaming video data. Therefore, FPD-Link III even further reduces cable cost by eliminating cables for control channels such as I2C and CAN bus.
FPD-Link III's embedded control channel uses the I2C bus protocol between the source and destination in the first implementations. (However, it is not limited to I2C.) The I2C master can read and write to all the slaves on the other side of the FPD-Link III chipset, which is effectively transparent to the I2C master and slaves communications. For example, this enables infotainment head units to control and configure displays, and image processing units to control and configure cameras using the same twisted pair cable as the data transmission.
The Digital Content Protection LLC approved FPD-Link III in 2009 as a high-bandwidth interface for carrying content whose owner wants HDCP security. This approval enables the FPD-Link III chipsets to include the highly confidential HDCP keys and state machines to encrypt the content. The embedded control channel in the FPD-Link III chipsets simplifies the key exchange protocols between the source and destinations that verify the destination is secure.
An additional new feature, FPD-Link III stops using LVDS technology and uses only CML for the serialized high-speed signals. This enables it to easily work at data rates greater than 3 Gbit/s on cables greater than 10 m long. An additional benefit for using CML is the coax-cable drive capability. The CML technology works well when driving the single conductor in coax cables. Since coax cables are very good at controlling impedance and noise, they reduce the need for differential signaling, which better tolerates impedance discontinuities and noise interference.
Another added benefit for FPD-Link III is the adaptive equalization built into the deserializer. The input signal to the deserializer usually has diminished integrity. This typically results from the Intersymbol interference (ISI) due to cable loss. The adaptive equalizer can sense the poor signal and restore it to the original integrity. This feature is useful in every application where the cable can vary in length, operating temperature, and humidity because these variables affect the ISI resulting from the low-pass filter effect of the cable.
- Display controller – IC that produces the signal
- Display Serial Interface (DSI)
- Embedded DisplayPort