Talk:Complex instruction set computer
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The tenses are a bit odd here. Maybe they should be unified to present tense unless past tense is actually approriate? —Preceding unsigned comment added by Qbeep (talk • contribs) 01:26, 9 April 2009 (UTC)
Is the date ("1994-10-10") at the bottom of the page really necessary? It is the date from the FOLDOC entry that this article is based on, I think. I don't see why it is still relevant. I'm going to remove it, but if it's serving some sort of good purpose, go ahead and put it back. James Foster 09:57, 24 Nov 2004 (UTC)
"For example, on one processor it was discovered that it was possible to improve performance by not using the procedure call instruction but using a sequence of simpler instructions instead."
Exactly what processor is the author refering to? Or did he just make that up? REFERENCES!!!
- The processor was probably the VAX, and the call instruction was probably either CALLG or CALLS. I remember this being discussed ages ago in the early days of modern RISC. Unfortunately, I don't have a reference right now - either it's not available to Google or it's buried in the welter of pages that match a search for "vax performance callg calls jsr" - but I suspect a reference can be found. I'll keep looking (or you, or somebody else, might find it). Guy Harris 07:08, 1 February 2006 (UTC)
- I found a similar example with the VAX-11/780 index instruction being slower than an equivalent, simpler instruction sequence. See: http://www.pattosoft.com.au/jason/Articles/HistoryOfComputers/1970s.html (third to last paragraph). This is also mentioned in the book "Computer Organization & Design" by Patterson and Hennessy, 1st Edition (page 350). If you can't find the reference for your original example, perhaps you can use this and link to the webpage I mentioned. Rogerbrent 18:40, 1 February 2006 (UTC)
I don't know. I added Tanenbaum's Structured Computing Organization book I used in my assembly class 2 years back, as the section on page 58-59 supports most of this article.Flying Bishop (talk) 15:49, 9 May 2009 (UTC)
CDC 6600 a CISC machine?
This article gives it as an example of a CISC processor, but the CDC 6600 page says "The basis for the 6600 CPU is what we would today refer to as a RISC system, one in which the processor is tuned to do instructions which are comparatively simple and have limited and well defined access to memory." It did, as I remember, have fixed-length instructions, only simple addressing modes, and a load/store architecture, which sounds more RISCy than CISCy; how does it qualify as a CISC processor? Guy Harris 19:33, 19 February 2006 (UTC)
No. It does not qualify as a CISC processor. I removed the reference.--Wws 18:08, 30 October 2006 (UTC)
Dave Patterson (and John Hennessey) cite the 6600 as a precursor to model RISC. See the referenced note paper (Dave said to do this). But other later CDC Cyber series, say 203 and 205, might be considered CISC or even VCISC. 126.96.36.199 (talk) 22:32, 23 March 2012 (UTC)
Goals and Differences
The nature of RISC is not only that it uses simple instructions but that it keeps the chip simple. CISC makes no effort to simplify the chip-- going for speed and capability and only using simplicity when it’s faster.
In the development of architectures, the term RICH meant Rich Instruction CHip, implying individual machine instructions were potentially extremely powerful, sometimes competing with compiler instructions. In the 1980s, CISC supplanted RICH in the trade press, although I consider RICH a more descriptive (and mroe clever) acronym than CISC.
This deserves mention within the CISC article, although I don't believe RICH deserves a separate article.
CISC vs RISC
Not all CISCs are microcoded or have "complex" instructions (compared to a Z80, the MIPS's 32-bit divide or any RISC floating-point instructions are extremely complex) and it's not the number of instructions nor the complexity of the implementation or of the instructions themselves that distinguish a CISC from a RISC, but the addressing modes and memory access. CISC is a catch-all term meaning anything that's not a load-store (RISC) architecture. A PDP-10, a PDP-8, an Intel 386, an Intel 4004, a Motorola 68000, a System z mainframe, a Burroughs B5000, a VAX, a Zilog Z80000, and a 6502 all vary wildly in the number, sizes, and formats of instructions, the number, types, and sizes of registers, and the available data types. Some have hardware support for operations like scanning for a substring, arbitrary-precision BCD arithmetic, or computing an arctangent, while others have only 8-bit addition and subtraction. But they are all CISC because they have "load-operate" instructions that read from memory and perform a calculation at the same time. The PDP-8, having only 8 fixed-length instructions and no microcode at all, is a CISC because of how the instructions work (for example, fetching from memory and computing an addition at once), but PowerPC, which has over 230 instructions (more than some VAXes) and complex internals like register renaming and a reorder buffer is a RISC. This Minimal CISC has 8 instructions, but is clearly a CISC because it combines memory access and computation in the same instructions. 188.8.131.52 (talk) 08:51, 30 May 2011 (UTC)
- I agree fully, but read the "definition" in the intro (last major edit by myself). I cannot see that it contradicts your points in any way really. However, I find your text well put, almost fit for inclusion in the article already as it stands here. 184.108.40.206 (talk) 00:04, 3 June 2011 (UTC)
Most of the discussion on this page is about historical machines, but shouldn't there be something about how CISC was succeeded by RISC because of the emphasis on pipelining for efficiency, the failure of compiler writers to generate machine code that actually utilized the more complicated CISC instruction, and that the CISC architectures violated Amdahl's law in terms of the biggest bang for the buck? — Preceding unsigned comment added by 220.127.116.11 (talk) 05:49, 30 December 2013 (UTC)
- Given that the primary instruction set architecture for desktop and laptop personal computers, and two of the significant instruction set architectures for servers, are CISC, I'm not sure it was fully "succeeded" by RISC, although the primary instruction set architecture for smartphones and tablets is RISC, and a lot of embedded computing uses various RISC architectures.
- The section "The RISC idea" does mention pipelining; the point about compilers not using some aspects of CISC is mentioned in the "Hardware utilization" section of the reduced instruction set computing article.
- Amdahl's law doesn't seem to say anything about bang-for-the-buck; it discusses the speedup available for a particular program from parallelizing it (which applies to CISC or RISC).
Instead of saying that CISC was succeeded, it would have been more accurate to have said that CISC was succeeded by RISC in the development of modern architectures, and that legacy architectures stopped executing CISC instructions directly and started breaking up the CISC instructions into RISC "micro-operations" as part of their execution. The Intel x86 and the IBM360 architectures fall in this category. The presence of these legacy architectures in desktops, servers, and mainframes is true, but I think that they are RISC systems that have a preprocessor in order to support CISC legacy code. Conceptually speaking, CISC is not a competitor to RISC for the reasons stated above. Amdahl's Law is very important in pipelining, but its general form says that the maximum expected improvement to an overall system is constrainted when only part of the system is improved. Thus devoting logic on a chip to CISC instructions is a poor choice when they are seldom used (due to compilers) and they can not be pipelined (due to widely varying execution times). Basically I think the section fails to mention that RISC won the CISC/RISC war. — Preceding unsigned comment added by 18.104.22.168 (talk) 19:42, 3 January 2014 (UTC)
- Given that programmers can't write uop code for x86 or z/Architecture, and compilers can't write uop code for x86 or z/Architecture, the "legacy" architectures are still relevant.
- As for how RISCy the micro-operations are, note that, with micro-operation fusion, the micro-operations aren't quite as micro; that page speaks of combining a compare instruction and a conditional branch into a single micro-op and of combining the load and add micro-ops of ADD [mem], EAX into a single micro-op. The latter is a bit of a move away from the load-store architecture aspect of RISC.
- So the only way in which RISC "won" is that the units of dispatch, scheduling, and execution in modern processors are simpler than some of the instructions in current CISC processors; the units of generated code, however, are still CISC in those processors, even if compilers only use some of the CISCy parts (memory-register and register-memory arithmetic, double-indexing in memory operands, maybe CISCier procedure calls in some cases, maybe decimal and string instructions on z/Architecture or REP/xxx instruction pairs on x86) and ignore the other CISCy parts (which don't get a lot of transistors allocated to them), and even some of the units of dispatch, scheduling, and execution might combine a memory reference and an arithmetic op (micro-operation fusion).
- The only RISC ISA that "won", for general-purpose computing, to the extent of displacing competitors or keeping them out in the first place is ARM (not a lot of Atom smartphones or tablets out there); the others lost in the desktop/laptop market (it'll be interesting to see whether ARM comes back there) and are fighting it out with x86-64 and z/Architecture in the server market. The others lost in the desktop/laptop market largely because Intel (and, to a lesser extent, AMD) had the money to throw transistors at decoders that turned x86 instructions into uop sequences; devoting logic on a chip to doing that is a very good choice if it means that you keep PowerPC, MIPS, SPARC, and PA-RISC out of a lucrative market.
- Another way to think of it is that the first "C" of "CISC" got split into "the stuff that we need to make go fast, because programmers and compilers use it a lot" and "the stuff that's not used enough, so it just has to work, not go fast", with the former stuff made to "go fast" with techniques such as breaking it into uops, and the latter stuff left around, but with the fraction of the chip used to implement it getting smaller over time. That split is a win for some of the ideas that motivated RISC, but with the "reduction" process not, for example, requiring a load-store architecture. Guy Harris (talk) 22:29, 3 January 2014 (UTC)
instructions or operations?
Seems to me that in place of "instruction", the CISC article should generally be using the term "opcode" or "operation specified by an opcode". Not all machines have only one opcode per instruction, and it seems to me that the mere fact that an architecture allows for multiple opcodes per instruction should not force it to be labeled as CISC. In other words, if load, add, and store require separate opcodes, the machine should be labeled as RISC, even if the architecture allows all three of those opcodes to appear together in the same instruction. So I would propose wording like this:
- a computer in which a single operation (dictated by a single opcode) can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modes within single operations.
or, how about this more concise statement:
- a computer in which a single operation (dictated by a single opcode) can execute a load from memory, an operation on the loaded data, and a store of the result.
- Ok, what are your definitions of "operation", "opcode", and "instruction" here? Is an "opcode" what is specified by the Wikipedia page:
- In computer science, an opcode (operation code) is the portion of a machine language instruction that specifies the operation to be performed.
- or is it something else? Is an "operation" something specified by an opcode, or is it a low-level operation? Guy Harris (talk) 00:25, 26 August 2011 (UTC)
- "a computer in which a single operation (dictated by a single opcode) can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modes within single operations" uses "operation" in two separate senses, so it's potentially confusing. "a computer in which a single operation (dictated by a single opcode) can execute a load from memory, an operation on the loaded data, and a store of the result" is better, although it seems to imply that, to be a CISC processor, you have to be able to do a load and a store in a single machine operation, and a lot of CISCs don't do that. I might be tempted to just change the opening sentence to say "where single machine operations (specified by a single opcode) can execute several low-level operations ... and/or are capable of multi-step operations or addressing modes within single machine operations", i.e. just replace "instruction" by "machine operation" and, the first time "machine operation" is used, note that a "machine operation" is what's specified by a single opcode. Guy Harris (talk) 18:56, 15 September 2011 (UTC)