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45 nm process

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Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future

Per the International Technology Roadmap for Semiconductors, the 45 nm MOSFET technology node should refer to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame.

Matsushita and Intel started mass-producing 45 nm chips in late 2007, and AMD started production of 45 nm chips in late 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. At the end of 2008, SMIC was the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM. In 2008, TSMC moved on to a 40 nm process.

Many critical feature sizes are smaller than the wavelength of light used for lithography (i.e., 193 nm and 248 nm). A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning has also been introduced to assist in shrinking distances between features, especially if dry lithography is used. It is expected that more layers will be patterned with 193 nm wavelength at the 45 nm node. Moving previously loose layers (such as Metal 4 and Metal 5) from 248 nm to 193 nm wavelength is expected to continue, which will likely further drive costs upward, due to difficulties with 193 nm photoresists.

High-κ dielectric

Chipmakers have initially voiced concerns about introducing new high-κ materials into the gate stack, for the purpose of reducing leakage current density. As of 2007, however, both IBM and Intel have announced that they have high-κ dielectric and metal gate solutions, which Intel considers to be a fundamental change in transistor design.[1] NEC has also put high-κ materials into production.

Technology demos

  • In 2004, TSMC demonstrated a 0.296-square-micrometre 45 nm SRAM cell. In 2008, TSMC moved on to a 40 nm process.[2]
  • In January 2006, Intel demonstrated a 0.346-square-micrometre 45 nm node SRAM cell.
  • In April 2006, AMD demonstrated a 0.370-square-micrometre 45 nm SRAM cell.
  • In June 2006, Texas Instruments debuted a 0.24-square-micrometre 45 nm SRAM cell, with the help of immersion lithography.
  • In November 2006, UMC announced that it had developed a 45 nm SRAM chip with a cell size of less than 0.25-square-micrometre using immersion lithography and low-κ dielectrics.
  • In 2006, Samsung developed a 40 nm process.[3]

The successors to 45 nm technology are 32 nm, 22 nm, and then 14 nm technologies.

Commercial introduction

Matsushita Electric Industrial Co. started mass production of system-on-a-chip (SoC) ICs for digital consumer equipment based on 45 nm process technology in June 2007.

Intel shipped its first 45 nm processor, the Xeon 5400 series, in November 2007.

Many details about Penryn appeared at the April 2007 Intel Developer Forum. Its successor is called Nehalem. Important advances[4] include the addition of new instructions (including SSE4, also known as Penryn New Instructions) and new fabrication materials (most significantly a hafnium-based dielectric).

AMD released its Sempron II, Athlon II, Turion II and Phenom II (in generally increasing order of performance), as well as Shanghai Opteron processors using 45 nm process technology in late 2008.

The Xbox 360 S, released in 2010, has a Xenon processor fabricated in a 45 nm process.[5]

The PlayStation 3 Slim model introduced the Cell Broadband Engine in a 45 nm process.[6]

Example: Intel's 45 nm process

At IEDM 2007, more technical details of Intel's 45 nm process were revealed.[7]

Since immersion lithography is not used here, the lithographic patterning is more difficult. Hence, a line-cutting double patterning method is used explicitly for this 45 nm process. Also, the use of high-κ dielectric dielectrics is introduced for the first time, to address gate leakage issues. For the 32 nm node, immersion lithography will begin to be used by Intel.

  • 160 nm gate pitch (73% of 65 nm generation)
  • 200 nm isolation pitch (91% of 65 nm generation) indicating a slowing of scaling of isolation distance between transistors
  • Extensive use of dummy copper metal and dummy gates[8]
  • 35 nm gate length (same as 65 nm generation)
  • 1 nm equivalent oxide thickness, with 0.7 nm transition layer
  • Gate-last process using dummy polysilicon and damascene metal gate
  • Squaring of gate ends using a second photoresist coating[9]
  • 9 layers of carbon-doped oxide and Cu interconnect, the last being a thick "redistribution" layer
  • Contacts shaped more like rectangles than circles for local interconnects
  • Lead-free packaging
  • 1.36 mA/μm nFET drive current
  • 1.07 mA/μm pFET drive current, 51% faster than 65 nm generation, with higher hole mobility due to increase from 23% to 30% Ge in embedded SiGe stressors

In a 2008 Chipworks reverse-engineering,[10] it was disclosed that the trench contacts were formed as a "Metal-0" layer in tungsten serving as a local interconnect. Most trench contacts were short lines oriented parallel to the gates covering diffusion, while gate contacts where even shorter lines oriented perpendicular to the gates.

It was recently revealed[11] that both the Nehalem and Atom microprocessors used SRAM cells containing eight transistors instead of the conventional six, in order to better accommodate voltage scaling. This resulted in an area penalty of over 30%.

Processors using 45 nm technology

References

  1. ^ "IEEE Spectrum: The High-k Solution". Archived from the original on 26 October 2007. Retrieved 25 October 2007.
  2. ^ "40nm Technology". TSMC. Retrieved 30 June 2019.
  3. ^ "History". Samsung Electronics. Samsung. Retrieved 19 June 2019.
  4. ^ "Report on Penryn Series Improvements" (PDF). Intel. October 2006.
  5. ^ "New Xbox 360 gets official at $299, shipping today, looks angular and ominous (video hands-on!)". AOL Engadget. 14 June 2010. Archived from the original on 17 June 2010. Retrieved 11 July 2010..
  6. ^ "Sony answers our questions about the new PlayStation 3". Ars Technica. 18 August 2009. Retrieved 19 August 2009..
  7. ^ Mistry, K.; Allen, C.; Auth, C.; Beattie, B.; Bergstrom, D.; Bost, M.; Brazier, M.; Buehler, M.; Cappellani, A.; Chau, R.; Choi, C.-H.; Ding, G.; Fischer, K.; Ghani, T.; Grover, R.; Han, W.; Hanken, D.; Hattendorf, M.; He, J.; Hicks, J.; Huessner, R.; Ingerly, D.; Jain, P.; James, R.; Jong, L.; Joshi, S.; Kenyon, C.; Kuhn, K.; Lee, K.; Liu, H.; Maiz, J.; Mclntyre, B.; Moon, P.; Neirynck, J.; Pae, S.; Parker, C.; Parsons, D.; Prasad, C.; Pipes, L.; Prince, M.; Ranade, P.; Reynolds, T.; Sandford, J.; Shifren, L.; Sebastian, J.; Seiple, J.; Simon, D.; Sivakumar, S.; Smith, P.; Thomas, C.; Troeger, T.; Vandervoorn, P.; Williams, S. & Zawadzki, K. (December 2007). "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging". 2007 IEEE International Electron Devices Meeting: 247–250. doi:10.1109/IEDM.2007.4418914. ISBN 978-1-4244-1507-6. S2CID 12392861.
  8. ^ Intel Pushes Lithography Limits, Part II
  9. ^ "Intel 45 nm process at IEDM". Archived from the original on 2 December 2008. Retrieved 2 September 2008.
  10. ^ "analysis". Archived from the original on 2 December 2008. Retrieved 15 March 2008.
  11. ^ 8T SRAM used for Nehalem and Atom
  12. ^ "Panasonic starts to sell a New-generation UniPhier System LSI". Panasonic. 10 October 2007. Retrieved 2 July 2019.
Preceded by
65 nm 		CMOS manufacturing processes Succeeded by
32 nm
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