Tejas was a code name for Intel's microprocessor which was to be a successor to the latest Pentium 4 with the Prescott core. Jayhawk was a code name for its Xeon counterpart. The cancellation of the processors in May 2004 underscored Intel's historical transition of its focus on single-core processors to multi-core processors.
In early 2003, Intel showed the design of Tejas and a plan to release it sometime in 2004, but put it off to 2005 later. Intel, however, announced it canceled the development on May 7, 2004. Analysts attribute the delay and eventual cancellation to the heat problems due to the extreme power consumption of the core, as that was the case in development of Prescott and its mediocre performance increase over Northwood. This cancellation reflected Intel's intention to focus on dual-core chips for the Itanium platform. With respect to desktop processors, Intel's development efforts shifted to the Pentium M microarchitecture (itself a derivative of the P6 microarchitecture) used in the Centrino notebook platform, which offered a processing power to power consumption ratio considerably higher than that offered by Prescott and other NetBurst based designs. The outcome of these development efforts was the Intel Core processor line, and later the Intel Core 2 line, providing and building on the benefits of Pentium M and offering Intel's first native dual core products for desktops and laptops.
This transition marks the end of the NetBurst line of CPU development from Intel that started back with the original Pentium 4.
Tejas and Jayhawk were to make several improvements on the Pentium 4's NetBurst microarchitecture. Tejas was to originally be built on a 90 nm process, later moving to a 65 nm process. The 90 nm version of the processor was reported to have 1 MB L2 cache, while the 65 nm chip would increase the cache to 2 MB. There was also to be a dual core version of Tejas called Cedarmill (or Cedar Mill depending on the source). This Cedarmill should not be confused with the 65 nm Cedar Mill-based Pentium 4, which appears to be what the codename was recycled for. The trace cache capacity would likely have been increased, and the number of pipeline stages was increased to between 40 and 50 stages. There would have been an improved version of Hyper-Threading, as well as a new version of SSE, which was later backported to the Intel Core 2 series after Tejas's cancellation and named SSSE3. Tejas was slated to operate at frequencies of 7 GHz or higher. However, it's likely that Tejas wouldn't have had linear performance scaling, as it would on average have executed fewer instructions per clock cycle due to more pipeline bubbles from branch mispredicts and data cache misses. Also, it would have run hotter as well with a TDP much higher than the Prescott core of Pentium 4. The CPU was cancelled late in its development after it had reached its tapeout phase.