10 nm process: Difference between revisions
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{{CMOS manufacturing processes}} |
{{CMOS manufacturing processes}} |
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The '''11 nanometer (11 nm) node''' is the technology node following [[16 nanometer|16 nm]] node. The exact naming of this technology node comes from the [[International Technology Roadmap for Semiconductors]] (ITRS). According to the 2007 edition of this roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a [[DRAM]] should be 11 [[Nanometer|nm]], although Intel's "Architecture and Silicon Cadence Model" places |
The '''11 nanometer (11 nm) node''' is the technology node following [[16 nanometer|16 nm]] node. The exact naming of this technology node comes from the [[International Technology Roadmap for Semiconductors]] (ITRS). According to the 2007 edition of this roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a [[DRAM]] should be 11 [[Nanometer|nm]], although Intel's "Architecture and Silicon Cadence Model" places its 11 nm node closer to the year 2015. Intel's [[Pat Gelsinger]] claims that Intel sees a 'clear way' towards the 11 nm node.<ref> [http://www.crn.com/hardware/208801780 Intel's Gelsinger Sees Clear Path To 10nm Chips] </ref><ref> [http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=209400807 MIT: Optical lithography good to 12 nanometers] </ref> At the 11 nm node in 2015, Intel expects to use a half-pitch of around 21 nm.<ref> Y. Borodovsky, Proc. SPIE 6153 (2006).</ref> This design rule is likely to be realized by [[double patterning]].<ref> J. Word ''et al.'', Proc. SPIE 6925 (2008).</ref> |
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While the roadmap has been based on the continuing extension of [[CMOS]] technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a [[monolayer]] or even less. Reported estimates indicate that transistors at these dimensions are significantly affected by [[quantum tunneling]].<ref name="Inq">{{cite news |url=http://web.archive.org/web/20070709210058/http://news.zdnet.com/2100-9584_22-5112061.html |title=Intel scientists find wall for Moore's Law |publisher=ZDNet |date=[[December 1]], [[2003]]}}</ref> As a result, non-silicon extensions of CMOS, using [[compound semiconductor|III-V]] materials or [[nanotubes]]/[[nanowires]], as well as non-CMOS platforms, including [[molecular electronics]], [[spintronics|spin-based computing]], and [[single-electron transistor|single-electron devices]], have been proposed. Hence, this node marks the practical beginning of [[nanoelectronics]]. |
While the roadmap has been based on the continuing extension of [[CMOS]] technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a [[monolayer]] or even less. Reported estimates indicate that transistors at these dimensions are significantly affected by [[quantum tunneling]].<ref name="Inq">{{cite news |url=http://web.archive.org/web/20070709210058/http://news.zdnet.com/2100-9584_22-5112061.html |title=Intel scientists find wall for Moore's Law |publisher=ZDNet |date=[[December 1]], [[2003]]}}</ref> As a result, non-silicon extensions of CMOS, using [[compound semiconductor|III-V]] materials or [[nanotubes]]/[[nanowires]], as well as non-CMOS platforms, including [[molecular electronics]], [[spintronics|spin-based computing]], and [[single-electron transistor|single-electron devices]], have been proposed. Hence, this node marks the practical beginning of [[nanoelectronics]]. |
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Revision as of 04:28, 3 June 2009
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MOSFET scaling (process nodes) |
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The 11 nanometer (11 nm) node is the technology node following 16 nm node. The exact naming of this technology node comes from the International Technology Roadmap for Semiconductors (ITRS). According to the 2007 edition of this roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm, although Intel's "Architecture and Silicon Cadence Model" places its 11 nm node closer to the year 2015. Intel's Pat Gelsinger claims that Intel sees a 'clear way' towards the 11 nm node.[1][2] At the 11 nm node in 2015, Intel expects to use a half-pitch of around 21 nm.[3] This design rule is likely to be realized by double patterning.[4]
While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Reported estimates indicate that transistors at these dimensions are significantly affected by quantum tunneling.[5] As a result, non-silicon extensions of CMOS, using III-V materials or nanotubes/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics.
Due to the extensive use of ultra-low-k dielectrics such as spin-on polymers or other porous materials, it is unlikely conventional lithography, etch or even chemical-mechanical polishing processes can continue to be used, because these materials contain a high density of voids or gaps. At scales of ~10 nm, quantum tunneling, especially through gaps, becomes a significant phenomenon.[6] Controlling gaps on these scales by means of electromigration can produce interesting electrical properties themselves.[7]
References
- ^ Intel's Gelsinger Sees Clear Path To 10nm Chips
- ^ MIT: Optical lithography good to 12 nanometers
- ^ Y. Borodovsky, Proc. SPIE 6153 (2006).
- ^ J. Word et al., Proc. SPIE 6925 (2008).
- ^ "Intel scientists find wall for Moore's Law". ZDNet. December 1, 2003.
{{cite news}}: Check date values in:|date=(help) - ^ Y. Naitoh et al., MRS Symposium Proceedings vol. 997 (2007).
- ^ S. Kayashima et al., Jap. J. Appl. Phys. vol. 46, L907-909 (2007).
| Preceded by 16 nm |
CMOS manufacturing processes | Succeeded by Nanoelectronics |
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