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Electronic Design Automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. This is sometimes referred to as ECAD (electronic computer-aided design) or just CAD. (The articles for Printed circuit boards and wire wrap both contain specialized discussions of the EDA used for those.)

Terminology

The term EDA is also used as an umbrella term for computer-aided engineering, computer-aided design and computer-aided manufacturing of electronics in the discipline of Electronic engineering. This usage probably originates in the IEEE Design Automation Technical Committee.

This article describes EDA specifically for electronics, and concentrates on EDA used for designing integrated circuits. The segment of the industry that must use EDA are chip designers at semiconductor companies. Large chips are too complex to design by hand.

Growth of EDA

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology^{[citation needed]}) Some users are foundry operators, who operate the semiconductor fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs.

History

Before EDA, integrated circuits were designed by hand, and manually laid out. Some advanced shops used geometric software to generate the tapes for the Gerber photoplotter, but even those copied digital recordings of mechanically-drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually. The best known company from this era was Calma, whose GDSII format survives.

By the mid-70s, developers were starting to automate the design, and not just the drafting. The first placement and routing (Place and route) tools were developed. The proceedings of the Design Automation Conference cover much of this era.

The next era began more or less with the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980. This ground breaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a hundredfold increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. Often the chips were not just easier to lay out, but more correct as well, because their designs could be simulated more thoroughly before construction.

The earliest EDA tools were produced academically, and were in the public domain. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still widely used is the Espresso heuristic logic minimizer and Magic.

Another crucial development was the formation of MOSIS, a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic idea was to use reliable, low-cost, relatively low-technology IC processes, and pack a large number of projects per wafer, with just a few copies of each projects' chips. Cooperating fabricators either donated the processed wafers, or sold them at cost, seeing the program as helpful to their own long-term growth.

1981 marks the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard, Tektronix, and Intel, had pursued EDA internally. In 1981, managers and developers spun out of these companies to concentrate on EDA as a business. Daisy Systems, Mentor Graphics, and Valid Logic Systems were all founded around this time, and collectively referred to as DMV. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.

In 1986, Verilog, a popular high-level design language, was first introduced as a hardware description language by Gateway Design Automation. In 1987, the U.S. Department of Defense funded creation of VHDL as a specification language. Simulators quickly followed these introductions, permitting direct simulation of chip designs: executable specifications. In a few more years, back-ends were developed to perform logic synthesis.

Many of the EDA companies acquire small companies with software or other technology that can be adapted to their core business. Most of the market leaders are rather incestuous amalgamations of many smaller companies. This trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs ( on digital circuitry, many new tools incorporate analog design, and mixed systems. This is happening because there is now a trend to place entire electronic systems on a single chip.

Current digital flows are extremely modular (see Integrated circuit design, Design closure, and Design flow (EDA)). The front ends produce standardized design descriptions that compile into invocations of "cells,", without regard to the cell technology. Cells implement logic or other electronic functions using a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools. Analog EDA tools are much less modular, since many more functions are required, they interact more strongly, and the components are (in general) less ideal.

Product areas

EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing from design to mask generation. The following applies to chip/ASIC/FPGA construction but is very similar in character to the areas of printed circuit board design:

Design and Architecture: design the chip's schematics, output in Verilog, VHDL, SPICE and other formats.
Floorplanning: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
Logic synthesis: translation of a chip's abstract, logical RTL-description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate (boolean-logic) primitives.
Behavioral Synthesis, High Level Synthesis or Algorithmic Synthesis: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
Intelligent verification
Co-design: The concurrent design, analysis or optimization of two or more electronic systems. Usually the electronic systems belong to differing substrates such as multiple PCBs or Package and Chip co-design.
Intelligent testbench
IP cores: provide pre-programmed design elements.
EDA databases: databases specialized for EDA applications. Needed since historically general purpose DBs did not provide enough performance.
Simulation: simulate a circuit's operation so as to verify correctness and performance.
- Transistor Simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
- Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
- Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
- Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
Clock Domain Crossing Verification (CDC check): Similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
Formal verification, also model checking: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalence at the logical level.
Power analysis and optimization: optimizes the circuit to reduce the power required for operation, without affecting the functionality.
Place and route, PAR: (for digital devices) tool-automated placement of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent routing of the design, which adds wires to connect the components' signal and power terminals.
Static timing analysis: Analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
Transistor layout: (for analog/mixed-signal devices), sometimes called polygon pushing – a prepared-schematic is converted into a layout-map showing all layers of the device.
Design for Manufacturability: tools to help optimize a design to make it as easy and cheap as possible to manufacture.
Design closure: IC design has many constraints, and fixing one problem often makes another worse. Design closure is the process of converging to a design that satisfies all constraints simultaneously.
Analysis of substrate coupling.
Power network design and analysis
Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.
- Design rule checking, DRC – checks a number of rules regarding placement and connectivity required for manufacturing.
- Layout versus schematic, LVS – checks if designed chip layout matches schematics from specification.
- Layout extraction, RCX – extracts netlists from layout, including parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout.
Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
- Resolution enhancement techniques, RET – methods of increasing of quality of final photomask.
- Optical proximity correction, OPC – up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
- Mask generation – generation of flat mask image from hierarchical design.
Manufacturing Test
- Automatic test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.
- Built-in self-test, or BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design
- Design For Test, DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing.
Technology CAD, or TCAD, simulates and analyses the underlying process technology. Semiconductor process simulation, the resulting dopant profiles, and electrical properties of devices are derived directly from device physics.
Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.

Largest companies and their histories

Well before Electronic Design Automation, the use of computers to help with drafting tasks was well established, and software commercially available. For example, Calma, Applicon, and Computervision, established in the late 1960s, sold digitizing and drafting software used for ICs. Zuken Inc. in Japan, established in 1976, sold similar software for PC boards. While these tools were valuable, they did not help with the design portion of the process, which was still done by hand. Design Automation software was developed in the 70s, in academia and within large companies, but it was not until the early 1980s that software to help with the design portion of the process became commercially available.

In 1981, Mentor Graphics was founded by managers from Tektronix, Daisy Systems was founded largely by developers from Intel, and Valid Logic Systems by designers from Lawrence Livermore National Laboratory and Hewlett Packard. Meanwhile companies such as Calma and Zuken attempted to expand into the design, as well as the drafting, portion of the market.

When EDA started, analysts categorized these companies as a niche within the “computer aided design” market, primarily mechanical design drafting tools for conceptualizing bridges, buildings and automobiles. In a few years these fields diverged, and today no companies specialize in both mechanical and electrical design automation.

Cadence Design Systems was founded in the mid 1980s, specializing in physical IC design. Synopsys was founded about the same time frame to productize logic synthesis. Both have grown to be the largest full-line suppliers of EDA tools. Magma Design Automation was founded in 1997 to take advantage of the simplifications possible by building an IC design system from scratch.

Company	Location	Market Value (March 2009)	Logo
Synopsys	Mountain View, California	$2550 million	File:SynopsysLogo.png
Cadence Design Systems	San Jose, California	$991 million	File:Cadence logo.jpg
Mentor Graphics	Wilsonville, Oregon	$410 million
Zuken Inc.	Yokohama, Japan	$149 million	File:Zuken small2.png
Magma Design Automation	San Jose, California	$42 million

One of the top five EDA businesses by revenue is the EEsof EDA division of Agilent. EEsof (founded 1983) is part of the much larger Agilent ($11 billion market value October 2008).

References

http://www.staticfreesoft.com/documentsTextbook.html Computer Aids for VLSI Design by Steven M. Rubin - text is available on line.
Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3, 2006. A two volume book surveying the field of EDA for ICs.
Combinatorial Algorithms for Integrated Circuit Layout, by Thomas Lengauer, ISBN 3-5190-2110-2, Teubner Verlag, 1997.
The Electronic Design Automation Handbook, by Dirk Jansen et al., Kluwer Academic Publishers, ISBN 1-4020-7502-2, 2003, available also in German ISBN 3-446-21288-4 (2005), a 750 page book with basics on IC design and tool principles, covering the whole field.

@@ Line 4: / Line 4: @@
 [[Image:Kicad Pcbnew3D screenshot.jpg|thumb|right|200px|3D View. PCB layout Program (KICAD PCBnew).]]
 <!-- Image with inadequate rationale removed: [[Image:Mentor PADS PCB Layout.PNG|thumb|right|200px|PCB Layout Program (Mentor PADS)]] -->
-'''Electronic Design Automation''' ('''EDA''') is the category of tools for designing and producing electronic systems ranging from [[printed circuit board]]s (PCBs) to [[integrated circuit]]s.  This is sometimes referred to as ECAD (electronic [[computer-aided design]]) or just CAD. ([[Printed circuit boards]] and [[wire wrap]] both contain specialized discussions of the EDA used for those.)
+'''Electronic Design Automation''' ('''EDA''') is the category of tools for designing and producing electronic systems ranging from [[printed circuit board]]s (PCBs) to [[integrated circuit]]s.  This is sometimes referred to as ECAD (electronic [[computer-aided design]]) or just CAD. (The articles for [[Printed circuit boards]] and [[wire wrap]] both contain specialized discussions of the EDA used for those.)
 ==Terminology==
@@ Line 19: / Line 19: @@
 By the mid-70s, developers were starting to automate the design, and not just the drafting.  The first placement and routing ([[Place and route]]) tools were developed.  The proceedings of the [[Design Automation Conference]] cover much of this era.
-The next era began more or less with the publication of "Introduction to VLSI Systems" by [[Carver Mead]] and [[Lynn Conway]] in 1980.  This groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a hundredfold increase in the complexity of the chips that could be designed, with improved access to [[functional verification| design verification]] tools that used [[logic simulation]].  Often the chips were not just easier to lay out, but more correct as well, because their designs could be simulated more thoroughly before construction.
+The next era began more or less with the publication of "Introduction to VLSI Systems" by [[Carver Mead]] and [[Lynn Conway]] in 1980.  This ground breaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a hundredfold increase in the complexity of the chips that could be designed, with improved access to [[functional verification| design verification]] tools that used [[logic simulation]].  Often the chips were not just easier to lay out, but more correct as well, because their designs could be simulated more thoroughly before construction.
 The earliest EDA tools were produced academically, and were in the public domain.  One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still widely used is the [[Espresso heuristic logic minimizer]] and [[Magic (software)|Magic]].
@@ Line 38: / Line 38: @@
 * [[Floorplanning]]: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros.  (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
 * [[Logic synthesis]]: translation of a chip's abstract, logical [[Register transfer level|RTL]]-description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate ([[boolean]]-logic) primitives.
-* [[Behavioral Synthesis]], [[High Level Synthesis]] or [[Algorithmic Synthesis]]: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizeable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
+* [[Behavioral Synthesis]], [[High Level Synthesis]] or [[Algorithmic Synthesis]]: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
 * [[Intelligent verification]]
 *  '''Co-design''': The concurrent design, analysis or optimization of two or more electronic systems. Usually the electronic systems belong to differing substrates such as multiple PCBs or Package and Chip  co-design.
@@ Line 51: / Line 51: @@
 * [[Clock Domain Crossing Verification]] (CDC check): Similar to [[Lint programming tool|linting]], but these checks/tools specialize in detecting and reporting potential issues like data loss, [[Metastability in electronics|meta-stability]] due to use of multiple clock domains in the design.
 * [[Formal verification]], also [[model checking]]: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as [[deadlock]]) cannot occur.
-* [[Formal equivalence checking|Equivalence checking]]: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalency at the ''logical'' level.
+* [[Formal equivalence checking|Equivalence checking]]: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalence at the ''logical'' level.
 * [[Power optimization (EDA)|Power analysis and optimization]]: optimizes the circuit to reduce the power required for operation, without affecting the functionality.
 * [[Place and route]], PAR: (for digital devices) [[Placement (EDA)|tool-automated placement]] of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent [[Routing (EDA)|routing]] of the design, which adds wires to connect the components' signal and power terminals.