Turion 64: Difference between revisions
No edit summary |
Greyhound64 (talk | contribs) |
||
Line 17: | Line 17: | ||
* Power consumption ([[Thermal Design Point|TDP]]): 25/35 Watt max |
* Power consumption ([[Thermal Design Point|TDP]]): 25/35 Watt max |
||
* First release: [[March 10]], [[2005]] |
* First release: [[March 10]], [[2005]] |
||
* Clock rate: 1600, 1800, 2000, 2200 MHz |
* Clock rate: 1600, 1800, 2000, 2200, 2400 MHz |
||
** 25W [[Thermal Design Point|TDP]]: |
** 25W [[Thermal Design Point|TDP]]: |
||
*** MT-28: 1600 [[MHz]] (512 KB L2-Cache) |
*** MT-28: 1600 [[MHz]] (512 KB L2-Cache) |
||
Line 32: | Line 32: | ||
*** ML-37: 2000 MHz (1024 KB L2-Cache) |
*** ML-37: 2000 MHz (1024 KB L2-Cache) |
||
*** ML-40: 2200 MHz (1024 KB L2-Cache) |
*** ML-40: 2200 MHz (1024 KB L2-Cache) |
||
*** ML-42: 2400 MHz (512 KB L2-Cache) |
|||
*** ML-44: 2400 MHz (1024 KB L2-Cache) |
|||
==See also== |
==See also== |
Revision as of 16:15, 7 January 2006
Turion 64 is AMD's 64-bit mobile processor, intended to compete with Intel's Pentium M. It is compatible with AMD's Socket 754 and is equipped with 512 or 1024 KB of L2 cache, a 64-bit single channel on-die memory controller, and an 800MHz HyperTransport bus. A new socket for Turion 64 and other mobile AMD processors, known as Socket S, will arrive in 2006.
AMD Taylor
The long rumoured Taylor Dual Core followons to the original Lancaster Turions are due to arrive in Q1 of 2006. Information has only recently surfaced that Taylor will indeed appear initially in low TDP Socket S1, also known as Socket 638, and will feature additional power saving technologies, such as dynamic cache activation. Taylor core will also use DDR-II memory controller from the outset. As the release date draws near, more information should surface about the well guarded specifications, when some reports pinned the inital maximum frequencies to be somewhere between 2.20 and 2.66 GHz.
AMD Taylor will first appear on IBM's 90nm Silicon on insulator (SOI) process, but will migrate to 65nm, likely with Silicon-Germanium (SiGe) stressed process which was recently achieved through the combined effort of IBM and AMD, with 40% improvement over comparable 65nm processes.
Cores
Lancaster (90 nm SOI)
- L1 cache: 64 + 64 KB (data + instructions)
- L2 cache: 512 or 1024 KB, fullspeed
- MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Power Now!, NX Bit
- Socket 754, HyperTransport (800 MHz, HT800)
- VCore: 1.00V - 1.45V
- Power consumption (TDP): 25/35 Watt max
- First release: March 10, 2005
- Clock rate: 1600, 1800, 2000, 2200, 2400 MHz
See also
References
- Reuters news report on the announcement of the chips
- Physorg report on the chip becoming available
- PCworld Turion based notebooks review
- Turion64 Inside Story from Mobility Guru
- Acer Aspire 5020 Series Review from www.notebookreview.com
- Detailed review at www.anandtech.com
- Detailed review at www.gamepc.com by Chris Connolly, 4 April 2005
- The Register : AMD, IBM "stress" silicon for 65nm process, by Tony Smith
External links
Non-computing definitions
- Turion is also a winter bud of water vegetation.