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==Compact Modeling==
==Compact Modeling==
[[File:Different FinFET structures which can be modeled by BSIM-CMG.png|thumb|Different FinFET structures which can be modeled by BSIM-CMG.]]
[[File:Different FinFET structures which can be modeled by BSIM-CMG.png|thumb|Different FinFET structures which can be modeled by BSIM-CMG.]]
BSIMCMG106.0.0,<ref>{{cite web |url=http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG |title=BSIMCMG Model |publisher=UC Berkeley}}</ref> officially released on March 1, 2012 by UC Berkeley [[BSIM|BSIM Group]], is the first standard model for FinFETs. BSIM-CMG is implemented in [[Verilog-A]]. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping. The surface potentials at the source and drain ends are solved analytically with poly-depletion and quantum mechanical effects. The effect of finite body doping is captured through a perturbation approach. The analytic surface potential solution agrees with 2-D device simulation results well. If the channel doping concentration is low enough to be neglected, computational efficiency can be further improved by a setting a specific flag (COREMOD= 1).
BSIMCMG106.0.0,<ref>{{cite web |url=http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG |title=BSIMCMG Model |publisher=UC Berkeley}}</ref> officially released on March 1, 2012 by UC Berkeley [[BSIM|BSIM Group]], is the first standard model for FinFETs. BSIM-CMG is implemented in [[Verilog-A]]. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping. The surface potentials at the source and drain ends are solved analytically with poly-depletion and quantum mechanical effects. The effect of finite body doping is captured through a perturbation approach. The analytic surface potential solution agrees closely with the 2-D device simulation results. If the channel doping concentration is low enough to be neglected, computational efficiency can be further improved by a setting a specific flag (COREMOD= 1).


All the important Multi-Gate (MG) transistor behaviors are captured by this model. Volume inversion is included in the solution of the Poisson’s equation, hence the subsequent I-V formulation automatically captures the volume inversion effect. Analysis of the electro-static potential in the body of MG MOSFETs provided the model equation for the short channel effects (SCE). The extra electrostatic control from the end-gates (top/bottom gates) (triple or quadruple-gate) is also captured in the short channel model.
All the important Multi-Gate (MG) transistor behaviors are captured by this model. Volume inversion is included in the solution of the Poisson’s equation, hence the subsequent I-V formulation automatically captures the volume inversion effect. Analysis of the electro-static potential in the body of MG MOSFETs provided the model equation for the short channel effects (SCE). The extra electrostatic control from the end-gates (top/bottom gates) (triple or quadruple-gate) is also captured in the short channel model.

Revision as of 20:29, 18 October 2012

A dual gate MOSFET and schematic symbol

A multigate device or multiple gate field-effect transistor (MuGFET) refers to a MOSFET (metal–oxide–semiconductor field-effect transistor) which incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a Multiple Independent Gate Field Effect Transistor (MIGFET). Multigate transistors are one of several strategies being developed by CMOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's Law.[1]

Development efforts into multigate transistors have been reported by AMD, Hitachi, IBM, Infineon Technologies, Intel Corporation, TSMC, Freescale Semiconductor, University of California, Berkeley and others and the ITRS predicts that such devices will be the cornerstone of sub-32 nm technologies.[2] The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning. Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-k/metal gate materials.

Dual gate MOSFETs are commonly used in VHF mixers and in sensitive VHF front end amplifiers. They are available from manufacturers such as Motorola, NXP, and Hitachi.[3][4][5]

Industry need

Planar transistors have been the core of integrated circuits for several decades, during which the size of the individual transistors has steadily decreased. As the size decreases, planar transistors increasingly suffer from the undesirable short-channel effect, especially "off-state" leakage current, which increases the idle power required by the device.[6]

In a multigate device, the channel is surrounded by several gates on multiple surfaces, allowing more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced current in the "on" state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics.

Integration challenges

The primary challenges to integrating nonplanar multigate devices into conventional semiconductor manufacturing processes include:

  • Fabrication of a thin silicon "fin" tens of nanometers wide
  • Fabrication of matched gates on multiple sides of the fin

Varieties

Dozens of multigate transistor variants may be found in the literature. In general, these variants may be differentiated and classified in terms of architecture (planar vs. non-planar design) and number of channels/gates (2, 3, or 4).

Planar double-gate transistors

Planar double-gate transistors employ conventional planar (layer by layer) manufacturing processes to create double-gate devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures. In planar double-gate transistors the drain-source channel is sandwiched between two independently fabricated gate/gate oxide stacks. The primary challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates.[7]

Flexfet

Flexfet is a planar, independently-double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last flow. Flexfet is a true double-gate transistor in that (1) both the top and bottom gates provide transistor operation, and (2) the operation of the gates is coupled such that the top gate operation affects the bottom gate operation and vice versa.[8] Flexfet was developed, and is manufactured, by American Semiconductor, Inc.

FinFETs

A double-gate FinFET device.
An SOI FinFET MOSFET

The term FinFET was coined by University of California, Berkeley researchers (Profs. Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor) to describe a nonplanar, double-gate transistor built on an SOI substrate,[9] based on the earlier DELTA (single-gate) transistor design.[10] The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by a thin silicon "fin", which forms the body of the device. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device.

In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD, IBM, and Motorola describe their double-gate development efforts as FinFET development whereas Intel avoids using the term to describe their closely related tri-gate architecture.[11] In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates.

A 25-nm transistor operating on just 0.7 Volt was demonstrated in December 2002 by Taiwan Semiconductor Manufacturing Company. The "Omega FinFET" design, named after the similarity between the Greek letter "Omega" and the shape in which the gate wraps around the source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.

FinFET can also have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.[12]

In 2012, Intel has started using FinFETs for its future commercial devices. Although, recent leaks suggest that Intel's FinFET shape has an unusual shape of a triangle rather than a rectangular. It is speculated that this might be due to the fact that triangle has a higher structural strength and can be more reliably manufactured.[13]

Tri-gate transistors

File:Trigate.jpg
Schematic view (L) and SEM view (R) of Intel tri-gate transistors

Tri-gate or 3-D Transistor fabrication is used by Intel Corporation for the nonplanar transistor architecture used in Ivy Bridge processors. These transistors employ a single gate stacked on top of two vertical gates allowing for essentially three times the surface area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than current transistors. This allows up to 37% higher speed, or a power consumption at under 50% of the previous type of transistors used by Intel.[14][15]

Intel explains, "The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state (for performance), and as close to zero as possible when it is in the 'off' state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance)."[16] Intel has stated that all products after Sandy Bridge will be based upon this 3D design.

Intel was the first company to announce this technology. In September 2002,[17] Intel announced their creation of 'Triple-Gate Transistors' to maximize 'transistor switching performance and decreases power-wasting leakage'. A year later in September 2003, AMD announced it was working on similar technology at the International Conference on Solid State Devices and Materials.[18][19] No further announcements of this technology were made until Intel's announcement in May 2011 although it was stated at IDF 2011, that they demonstrated a working SRAM chip based on this technology at IDF 2009.[20]

On April 23, 2012 Intel released a new line of CPUs, termed Ivy Bridge, which feature tri-gate transistors.[21][22] Intel has been working on its tri-gate architecture since 2002, but it took until 2011 to work out mass production issues. The new style of transistor was described on May 4, 2011, in San Francisco.[23] Intel factories are expected to make upgrades over 2011 and 2012 to be able to manufacture the Ivy Bridge CPUs.[24] As well as being used in Intel's Ivy Bridge chips for desktop PCs, the new transistors will also be used in Intel's Atom chips for low powered devices.[23]

The term tri-gate is sometimes used generically to denote any multigate FET with three effective gates or channels.

Gate-all-around (GAA) FETs

Gate-all-around FETs are similar in concept to FinFETs except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates. Gate-all-around FETs have been successfully built around a silicon nanowire.[25] and etched InGaAs nanowires.[26]

Compact Modeling

Different FinFET structures which can be modeled by BSIM-CMG.

BSIMCMG106.0.0,[27] officially released on March 1, 2012 by UC Berkeley BSIM Group, is the first standard model for FinFETs. BSIM-CMG is implemented in Verilog-A. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping. The surface potentials at the source and drain ends are solved analytically with poly-depletion and quantum mechanical effects. The effect of finite body doping is captured through a perturbation approach. The analytic surface potential solution agrees closely with the 2-D device simulation results. If the channel doping concentration is low enough to be neglected, computational efficiency can be further improved by a setting a specific flag (COREMOD= 1).

All the important Multi-Gate (MG) transistor behaviors are captured by this model. Volume inversion is included in the solution of the Poisson’s equation, hence the subsequent I-V formulation automatically captures the volume inversion effect. Analysis of the electro-static potential in the body of MG MOSFETs provided the model equation for the short channel effects (SCE). The extra electrostatic control from the end-gates (top/bottom gates) (triple or quadruple-gate) is also captured in the short channel model.

See also

References

  1. ^ Risch, L. "Pushing CMOS Beyond the Roadmap", Proceedings of ESSCIRC, 2005, p. 63
  2. ^ http://www.itrs.net/Links/2006Update/FinalToPost/04_PIDS2006Update.pdf Table39b
  3. ^ [1]
  4. ^ [2]
  5. ^ [3]
  6. ^ Subramanian V (2010). "Multiple gate field-effect transistors for future CMOS technologies". IETE Technical Review. 27: 446–454.
  7. ^ Wong, H-S. Chan, K. Taur, Y. "Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel" IEDM 1997, p.427
  8. ^ Wilson, D.; Hayhurst, R.; Oblea, A.; Parke, S.; Hackler, D. "Flexfet: Independently-Double-Gated SOI Transistor With Variable Vt and 0.5V Operation Achieving Near Ideal Subthreshold Slope" SOI Conference, 2007 IEEE International
  9. ^ Huang, X. et al. (1999) "Sub 50-nm FinFET: PMOS" International Electron Devices Meeting Technical Digest, p. 67. December 5–8, 1999.
  10. ^ Hisamoto, D. et al. (1991) "Impact of the vertical SOI 'Delta' Structure on Planar Device Technology" IEEE Trans. Electron. Dev. 41 p. 745.
  11. ^ [4]
  12. ^ http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5715611&contentType=Journals+%26+Magazines&queryText%3DDual-+Independent-Gate+FinFETs+for+Low+Power+Logic+Circuits
  13. ^ http://www.eetimes.com/electronics-news/4373195/Intel-FinFETs-shape-revealed
  14. ^ Cartwright J (2011). "Intel enters the third dimension". Nature. doi:10.1038/news.2011.274.
  15. ^ Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium (ElectroIQ 2012)
  16. ^ "Below 22nm, spacers get unconventional: Interview with ASM". ELECTROIQ. Retrieved 2011-05-04.
  17. ^ http://digidownload.libero.it/kayk/Approfondimenti/Terahertz.pdf
  18. ^ http://www.zdnet.co.uk/news/processors/2003/09/19/amd-unveils-triple-gate-transistor-39116510/
  19. ^ http://www.xbitlabs.com/news/other/display/20030918140333.html
  20. ^ http://www.dailytech.com/IDF+2011+Intel+Looks+to+Take+a+Bite+Out+of+ARM+AMD+With+3D+FinFET+Tech/article22719.htm
  21. ^ Miller, Michael J. PC Magazine http://forwardthinking.pcmag.com/pc-hardware/296972-intel-releases-ivy-bridge-first-processor-with-tri-gate-transistor. {{cite news}}: Missing or empty |title= (help)
  22. ^ "Intel Reinvents Transistors Using New 3-D Structure". Intel. Retrieved 5/4/2011. {{cite web}}: Check date values in: |accessdate= (help)
  23. ^ a b "Transistors go 3D as Intel re-invents the microchip". Ars Technica. 5 May 2011. Retrieved 7 May 2011.
  24. ^ Murray, Matthew (4 May 2011). "Intel's New Tri-Gate Ivy Bridge Transistors: 9 Things You Need to Know". PC Magazine. Retrieved 7 May 2011.
  25. ^ Singh N; et al. (2006). "High-Performance fully depleted Silicon Nanowire Gate-All-Around CMOS devices". IEEE Electron Device Letters. 27 (5): 383–386. doi:10.1109/LED.2006.873381. {{cite journal}}: Explicit use of et al. in: |author= (help)
  26. ^ https://engineering.purdue.edu/~yep/Papers/IEDM_S33P02_GAA_Purdue.pdf
  27. ^ "BSIMCMG Model". UC Berkeley.
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