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In semiconductor manufacturing, 3 nanometer, usually abbreviated 3 nm, is the next die shrink after the 5 nanometer node. As of 2019, Samsung and TSMC have announced plans to put a 3nm semiconductor node into commercial production.

History

Research and technology demos

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center co-developed a 3 nm transistor, the world's smallest nanoelectronic device, based on finFET technology.^[1]^[2]

Commercialization history

In late 2016 TSMC announced plans to construct a 5nm-3nm node semiconductor fabrication plant with a co-commitment investment of around $15.7 billion US, with a tentative production date of 2022.^[3] In 2017 TSMC announced it was to begin construction of the 3nm semiconductor fabrication plant at the Tainan Science Park in Taiwan.^[4]

In early 2018, IMEC and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.^[5]

In early 2019 Samsung presented plans to manufacture 3nm GAAFET (Gate All-Around field effect transistors) at the 3nm node by 2021;^[6] Samsung's semiconduction roadmap also included products at 8, 7, 6, 5, and 4 nm 'nodes'.^[7]

After 3nm

The ITRS uses (2017) the terms "2.1nm", "1.5nm", and "1.0nm" as generic terms for the nodes after 3nm.^[8]^[9] "2 nanometer" (2nm) and "14 angstrom" (14Å) nodes have also been (2017) tentatively identified by An Steegen (of IMEC) as future production nodes after 3nm, with hypothesized introduction dates of ~2024, and beyond 2025 respectively.^[10]

In late 2018 TSMC chairman Mark Liu predicted chip scaling would continue to 3nm and 2nm nodes;^[11] however, as of 2019 other semiconductor specialists were undecided as to whether nodes beyond 3nm could become viable.^[12]

References

^ "Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012 {{citation}}: Unknown parameter |dead-url= ignored (|url-status= suggested) (help)
^ Lee, Hyunjin; et al. (2006), "Sub-5nm All-Around Gate FinFET for Ultimate Scaling", Symposium on VLSI Technology, 2006: 58–59, doi:10.1109/VLSIT.2006.1705215, ISBN 978-1-4244-0005-8
^ Patterson, Alan (12 Dec 2016), "TSMC Plans New Fab for 3nm", www.eetimes.com
^ Patterson, Alan (2 Oct 2017), "TSMC Aims to Build World's First 3-nm Fab", www.eetimes.com
^ "Imec and Cadence Tape Out Industry's First 3nm Test Chip", www.cadence.com (press release), 28 Feb 2018
^ Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", www.tomshardware.com
^ Armasu, Lucian (25 May 2017), "Samsung Reveals 4nm Process Generation, Full Foundry Roadmap", www.tomshardware.com
^ INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - EXECUTIVE SUMMARY (PDF), ITRS, 2017, Table ES2, p.18
^ INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017
^ Merritt, Rick (19 May 2017), "4 Views of the Silicon Roadmap - Distant hope for a 14-angstrom node", www.eetimes.com
^ Patterson, Alan (12 Sep 2018), "TSMC: Chip Scaling Could Accelerate", www.eetimes.com
^ Merritt, Rick (4 March 2019), "SPIE Conference Predicts Bumpy Chip Roadmap", www.eetasia.com

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Semiconductor device fabrication

MOSFET scaling (process nodes)
020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977 1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2025
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
v t e