In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 5 nanometer (5 nm) node as the technology node following the 7 nm node.
Transistors at the 7 nm scale were first produced by researchers in the first decade of the 21st century – the process scale may represent the end of Moore's Law scaling for electronic devices.
As of 2017, no 5 nm scale devices have been commercially produced.
The 5 nm node was once assumed by some experts to be the end of Moore's law. Transistors smaller than 7 nm will experience quantum tunnelling through their logic gates. Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the 2 years estimated by Moore's law.
Beyond 7 nm, major technological advances would have to be made; possible candidates include vortex laser, MOSFET-BJT dual-mode transistor, 3D packaging, microfluidic cooling, PCMOS, vacuum transistors, t-rays, extreme ultraviolet lithography, carbon nanotube transistors, silicon photonics, graphene, phosphorene, organic semiconductors, gallium arsenide, indium gallium arsenide, nano-patterning, and reconfigurable chaos-based microchips.
In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center codeveloped a 3 nm transistor, the world's smallest nanoelectronic device based on conventional technology, called a fin field-effect transistor (FinFET). It was the smallest transistor ever produced.
In 2008, transistors one atom thick and ten atoms wide were made by UK researchers. They were carved from graphene, a potential alternative to silicon as the basis of future computing. Graphene is a material made from flat sheets of carbon in a honeycomb arrangement, and is a leading contender. A team at the University of Manchester, UK, used it to make some of the smallest transistors at this time: devices only 1 nm across that contain just a few carbon rings.
In 2012, a single-atom transistor was fabricated using a phosphorus atom bound to a silicon surface (between two significantly larger electrodes). This transistor could be said to be a 180 picometer transistor, the Van der Waals radius of a phosphorus atom; though its covalent radius bound to silicon is likely smaller. Making transistors smaller than this will require either using elements with smaller atomic radii, or using subatomic particles—like electrons or protons—as functional transistors.
- "End of Moore's Law: It's not just about physics". CNET. August 28, 2013.
- Pirzada, Usman. "Intel ISSCC: 14nm all figured out, 10nm is on track, Moores Law still alive and kicking". WCCF Tech. Retrieved 2015-07-02.
- Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )
- Lee, Hyunjin; et al. (2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". Symposium on VLSI Technology, 2006: 58–59. doi:10.1109/VLSIT.2006.1705215.
- Atom-thick material runs rings around silicon
- Fuechsle, Martin; et al. (2010). "Spectroscopy of few-electron single-crystal silicon quantum dots". Nature Nanotechnology. 5 (7): 502–505. doi:10.1038/nnano.2010.95.
- Ng, Jansen (May 24, 2010). "Researchers Create Seven Atom Transistor, Working on Quantum Computer". Daily Tech.
- Beale, Bob (May 24, 2010). "Quantum leap: World's smallest transistor built with just 7 atoms". Phys.Org.
- Fuechsle, M.; Miwa, J. A.; Mahapatra, S.; Ryu, H.; Lee, S.; Warschkow, O.; Hollenberg, L. C. L.; Klimeck, G.; Simmons, M. Y. (2012). "A single-atom transistor". Nature Nanotechnology. 7 (4): 242. doi:10.1038/nnano.2012.21. PMID 22343383.
- "Team designs world's smallest transistor". Retrieved 28 May 2013.
- "IMEC and Cadence Disclose 5nm Test Chip". Retrieved 25 Nov 2015.
- "The Roadmap to 5nm: Convergence of Many Solutions Needed". Retrieved 25 Nov 2015.
- Mark LaPedus (2016-01-20). "5nm Fab Challenges".
Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
- Desai, S. B.; Madhvapathy, S. R.; Sachid, A. B.; Llinas, J. P.; Wang, Q.; Ahn, G. H.; Pitner, G.; Kim, M. J.; Bokor, J.; Hu, C.; Wong, H.- S. P.; Javey, A. (2016). "MoS". Science. American Association for the Advancement of Science (AAAS). 354 (6308): 99–102. doi:10.1126/science.aah4698.
- Yang, Sarah (2016-10-06). "Smallest. Transistor. Ever. | Berkeley Lab". News Center. Retrieved 2016-10-08.
- "Intel Outlines Process Technology Roadmap". Xbit. 2009-08-22.
- "インテル、32nmプロセスの順調な立ち上がりをアピール" [Intel touts steady rise of 32nm processors] (in Japanese). PC Watch. 2009-08-21.
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