5 nm process
In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nm process as the MOSFET technology node following the 7 nm node. In 2020, Samsung and TSMC entered volume production of 5 nm chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.
Quantum tunnelling effects through the gate oxide layer on 7 nm and 5 nm transistors become increasingly difficult to manage using existing semiconductor processes. Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.
In 2017, IBM revealed that they had created 5 nm silicon chips, using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2.
In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4. In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.
For their 5nm process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.
In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm2. In mid 2020 TSMC claimed its (N5) 5nm process offered 1.8x the density of its 7nm N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P) was claimed to improve on N5 with +5% speed or -10% power.
On October 13, 2020, Apple announced a new iPhone 12 lineup using the A14, together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, which were the first devices to be commercialized on TSMC's 5nm node. Later, on November 10, 2020, Apple also revealed three new Mac models using the Apple M1, another 5nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm2.
5 nm process nodes
|Samsung||TSMC||IRDS roadmap 2017|
|Process name (nm)||5LPE||N5||7||5|
|Transistor density (MTr/mm2)||127||173||?||?|
|SRAM bit-cell size (μm2)||0.026||0.017–0.019||0.027||0.020|
|Transistor gate pitch (nm)||57||48||48||42|
|Interconnect pitch (nm)||36||28||28||24|
|Risk production year||2018||2019||2019||2021|
Beyond 5 nm
3.5 nm has also been given as a name for the first node beyond 5 nm.
- Cutress, Dr Ian. "'Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5". www.anandtech.com. Retrieved 2020-08-28.
- "Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology". HPCwire. Retrieved 2020-08-28.
- "Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. Retrieved 2018-07-15.
- "IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. 2002-12-09. Retrieved 7 December 2017.
- Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting: 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. S2CID 10151651.
- "NEC test-produces world's smallest transistor". Thefreelibrary.com. Retrieved 7 December 2017.
- Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003: 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.
- "IMEC and Cadence Disclose 5nm Test Chip". Semiwiki.com. Retrieved 25 Nov 2015.
- "The Roadmap to 5nm: Convergence of Many Solutions Needed". Semi.org. Archived from the original on 26 November 2015. Retrieved 25 November 2015.
- Mark LaPedus (2016-01-20). "5nm Fab Challenges".
Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
- Sebastian, Anthony. "IBM unveils world's first 5nm chip". Ars Technica. Retrieved 2017-06-05.
- Zafar, Ramish (June 5, 2017). "It's Official: IBM Launches The 5nm GAAFET Chip With 30 Billion Transistors Per 50mm², 75% Power & 40% Performance Boost".
- "IBM Figures Out How to Make 5nm Chips". Uk.pcmag.com. 5 June 2017. Retrieved 7 December 2017.
- Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". anandtech.com. Retrieved 2019-05-31.
- TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology (press release), TSMC, 3 April 2019
- J. Kim et al., Proc. SPIE 11328, 113280I (2020).
- Solca, Bogdan. "TSMC already sampling Apple's 5 nm A14 Bionic SoCs for 2020 iPhones". Notebookcheck.
- Cutress, Dr Ian. "Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020". www.anandtech.com.
- Hruska, Joel (25 Aug 2020), "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond", www.extremetech.com
- Patel, Dylan (2020-10-27). "Apple's A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC's Density Claims". SemiAnalysis. Retrieved 2020-10-29.
- Jones, Scotten, 7nm, 5nm and 3nm Logic, current and projected processes
- Schor, David (2019-04-06). "TSMC Starts 5-Nanometer Risk Production". WikiChip Fuse. Retrieved 2019-04-07.
- "IRDS international roadmap for devices and systems 2017 edition" (PDF). Archived from the original (PDF) on 2018-10-25.
- Jones, Scotten (May 3, 2019). "TSMC and Samsung 5nm Comparison". Semiwiki. Retrieved 30 July 2019.
- INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017, Section 4.5 Table MM-10 (p.12) entries : "SRAM bitcell area (um2)" ; "SRAM 111 bit cell area density - Mbits/mm2", archived from the original (PDF) on 2018-10-25, retrieved 2018-10-24
- J. C. Liu et al., IEDM 2020.
- "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Semiconductors.org. Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.
- "5 nm lithography process". En.wikichip.org. Retrieved 7 December 2017.
- "15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". EETimes.com. 16 January 2017. Retrieved 4 June 2018.
7 nm (FinFET)
|MOSFET semiconductor device fabrication process||Succeeded by|