In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nanometer (5 nm) node as the MOSFET technology node following the 7 nm node. As of 2019, Samsung Electronics and TSMC have begun commercial production of 5 nm nodes.
5 nm nodes are based on multi-gate MOSFET (MuGFET) technology. The two types of MuGFET technology used at 5 nm are the FinFET (fin field-effect transistor) and the GAAFET (gate-all-around field-effect transistor).
The 5 nm node was once assumed by some experts to be the end of Moore's law. Transistors smaller than 7 nm will experience quantum tunnelling through the gate oxide layer. Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the two years estimated by Moore's law.
Beyond 7 nm, it was initially claimed that major technological advances would have to be made to produce chips at this small scale. In particular, it is believed[according to whom?] that 5 nm may usher in the successor to the FinFET, such as a gate-all-around architecture.
Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6 nanometer silicon-on-insulator (SOI) MOSFET.
In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4. In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.
5 nm process nodes
|Samsung ||TSMC ||IRDS roadmap 2017|
|Process name (nm)||5LPE||N5||7||5|
|Transistor density (MTr/mm2)||126.53||173.1||222 (37x6)  †||300 (50x6)  †|
|SRAM bit-cell size (µm²)||0.0262||0.017-0.019||0.0269||0.0202|
|Transistor gate pitch (nm)||57||48||48||42|
|Interconnect pitch (nm)||36||30||28||24|
|† Based on a 6T SRAM 111 cell|
Beyond 5 nm
3.5 nm has also been given as a name for the first node beyond 5 nm.
- "End of Moore's Law: It's not just about physics". CNET. August 28, 2013.
- "Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. Retrieved 2018-07-15.
- "Intel Outlines Process Technology Roadmap". Xbit. 2009-08-22. Archived from the original on 2011-05-28.
- "インテル、32nmプロセスの順調な立ち上がりをアピール" [Intel touts steady rise of 32 nm processors] (in Japanese). PC Watch. 2009-08-21.
- "IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. 2002-12-09. Retrieved 7 December 2017.
- Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting: 267–270. doi:10.1109/IEDM.2002.1175829.
- "NEC test-produces world's smallest transistor". Thefreelibrary.com. Retrieved 7 December 2017.
- Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003: 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446.
- "IMEC and Cadence Disclose 5nm Test Chip". Semiwiki.com. Retrieved 25 Nov 2015.
- "The Roadmap to 5nm: Convergence of Many Solutions Needed". Semi.org. Archived from the original on 26 November 2015. Retrieved 25 November 2015.
- Mark LaPedus (2016-01-20). "5nm Fab Challenges".
Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
- Sebastian, Anthony. "IBM unveils world's first 5nm chip". Ars Technica. Retrieved 2017-06-05.
- "IBM Figures Out How to Make 5nm Chips". Uk.pcmag.com. 5 June 2017. Retrieved 7 December 2017.
- "TSMC Breaks Ground on Fab 18 in Southern Taiwan Science Park".
- Shilov, Anton. "TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019".
- Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". anandtech.com. Retrieved 2019-05-31.
- TSMC and OIP Ecosystem Partners Deliver Industry’s First Complete Design Infrastructure for 5nm Process Technology (press release), TSMC, 3 April 2019
- Jones, Scotten, 7nm, 5nm and 3nm Logic, current and projected processes
- Schor, David (2019-04-06). "TSMC Starts 5-Nanometer Risk Production". WikiChip Fuse. Retrieved 2019-04-07.
- "IRDS international roadmap for devices and systems 2017 edition" (PDF).
- Jones, Scotten (May 3, 2019). "TSMC and Samsung 5nm Comparison". Semiwiki. Retrieved 30 July 2019.
- INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017
- "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Semiconductors.org. Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.
- "5 nm lithography process". En.wikichip.org. Retrieved 7 December 2017.
- "15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". EETimes.com. 16 January 2017. Retrieved 4 June 2018.
7 nm (FinFET)
|MOSFET manufacturing processes||Succeeded by|
3 nm (GAAFET)