5 nm process

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In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the nm process as the MOSFET technology node following the 7 nm node. In 2020, Samsung and TSMC entered volume production of 5 nm chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.[1][2]

The term "5 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[3][4]

History[edit]

Background[edit]

Quantum tunnelling effects through the gate oxide layer on 7 nm and 5 nm transistors became increasingly difficult to manage using existing semiconductor processes.[5] Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[6][7]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[8][9]

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.[10][11]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.[12]

In 2017, IBM revealed that it had created 5 nm silicon chips,[13] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2, for a total of 30 billion transistors.[14][15]

Commercialization[edit]

In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4.[16] In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.[17] For the expected 28 nm minimum metal pitch, SALELE is the proposed best patterning method.[18]

For their 5 nm process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.[19]

In October 2019, TSMC started sampling 5 nm A14 processors for Apple.[20]

In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their 5 nm test chips with a die size of 17.92 mm2.[21] In mid 2020 TSMC claimed its (N5) 5 nm process offered 1.8x the density of its 7 nm N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.[22]

On October 13, 2020, Apple announced a new iPhone 12 lineup using the A14, together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, which were the first devices to be commercialized on TSMC's 5 nm node. Later, on November 10, 2020, Apple also revealed three new Mac models using the Apple M1, another 5 nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm2.[23]

In October 2021, TSMC introduced a new member of its 5 nm process family: N4P. Compared to N5, the node offers 11% higher performance (6% higher vs N4), 22% higher power efficiency, 6% higher transistor density and lower mask count. TSMC expects first tapeouts by the second half of 2022.[24][25]

In December 2021, TSMC announced a new member of its 5 nm process family designed for HPC applications: N4X. The process features optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors. The process will offer up to 15% higher performance vs N5 (or up to 4% vs N4P) at 1.2 V and supply voltage in excess of 1.2 V. TSMC expects N4X to enter risk production by the first half of 2023.[26][27][28]

In June 2022, Intel presented some details about the Intel 4 process: the company's first process to use EUV, 2x higher transistor density compared to Intel 7, use of cobalt-clad copper for the finest five layers of interconnect, 21.5% higher performance at iso power or 40% lower power at iso frequency at 0.65 V compared to Intel 7 etc. Intel's first product to be fabbed on Intel 4 is Meteor Lake, powered on in Q2 2022 and scheduled for shipping in 2023.[29]

5 nm process nodes[edit]

IRDS roadmap 2017[30] Samsung[31][32][33][34] TSMC[31] Intel[35][29]
Process name 7 nm 5 nm 5LPE 4LPE N5 N5P N4 N4P N4X[26][27][28] 4
Transistor density (MTr/mm2) Un­known Un­known 133.56–134.9 137–145.7 185.46 196.6[31][36] Un­known 160
SRAM bit-cell size (μm2) 0.027[37] 0.020[37] 0.026 0.026 0.021 Un­known Un­known Un­known Un­known
Transistor gate pitch (nm) 48 42 57 57 48 Un­known Un­known Un­known 50
Interconnect pitch (nm) 28 24 36 32 28[38] Un­known Un­known Un­known 30
Release status 2019 2021 2018 risk production[16] 2020 risk production 2019 risk production[17] 2020 risk production 2021 risk production 2022 risk production Risk production by H1 2023 2022 risk production[39]
2023 production

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[40][41]

Beyond 5 nm[edit]

3 nm (3-nanometer) is the usual term for the next node after 5 nm. As of 2021, TSMC plans to commercialize the 3 nm node for 2022, while Samsung and Intel have plans for 2023.[35][42][43][44]

3.5 nm has also been given as a name for the first node beyond 5 nm.[45]

References[edit]

  1. ^ Cutress, Dr Ian. "'Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5". AnandTech. Retrieved 28 August 2020.
  2. ^ "Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology". HPCwire. Retrieved 28 August 2020.
  3. ^ "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". Retrieved 20 April 2020.
  4. ^ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Retrieved 20 April 2021.
  5. ^ "Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. Retrieved 15 July 2018.
  6. ^ "IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. 9 December 2002. Archived from the original on 31 May 2011. Retrieved 7 December 2017.{{cite web}}: CS1 maint: unfit URL (link)
  7. ^ Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). Extreme scaling with ultra-thin Si channel MOSFETs. Digest. International Electron Devices Meeting. pp. 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. S2CID 10151651.
  8. ^ "NEC test-produces world's smallest transistor". Thefreelibrary.com. Retrieved 7 December 2017.
  9. ^ Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). Sub-10-nm planar-bulk-CMOS devices using lateral junction control. IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.
  10. ^ "IMEC and Cadence Disclose 5nm Test Chip". Semiwiki.com. Retrieved 25 November 2015.
  11. ^ "The Roadmap to 5nm: Convergence of Many Solutions Needed". Semi.org. Archived from the original on 26 November 2015. Retrieved 25 November 2015.
  12. ^ Mark LaPedus (20 January 2016). "5nm Fab Challenges". Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
  13. ^ Sebastian, Anthony (5 June 2017). "IBM unveils world's first 5nm chip". Ars Technica. Retrieved 5 June 2017.
  14. ^ Huiming, Bu (5 June 2017). "5 nanometer transistors inching their way into chips". IBM.
  15. ^ "IBM Figures Out How to Make 5nm Chips". Uk.pcmag.com. 5 June 2017. Retrieved 7 December 2017.
  16. ^ a b Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". AnandTech. Retrieved 31 May 2019.
  17. ^ a b "TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology" (Press release). TSMC. 3 April 2019.
  18. ^ "SALELE Double Patterning for 7nm and 5nm Nodes". LinkedIn.
  19. ^ Jaehwan Kim; Jin Kim; Byungchul Shin; Sangah Lee; Jae-Hyun Kang; Joong-Won Jeon; Piyush Pathak; Jac Condella; Frank E. Gennari; Philippe Hurat; Ya-Chieh Lai (23 March 2020). Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes. Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280I. San Jose, California, United States. doi:10.1117/12.2551970.
  20. ^ Solca, Bogdan. "TSMC already sampling Apple's 5 nm A14 Bionic SoCs for 2020 iPhones". Notebookcheck.
  21. ^ Cutress, Dr Ian. "Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020". AnandTech.
  22. ^ Hruska, Joel (25 August 2020). "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond". ExtremeTech.
  23. ^ Patel, Dylan (27 October 2020). "Apple's A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC's Density Claims". SemiAnalysis. Retrieved 29 October 2020.
  24. ^ "TSMC Expands Advanced Technology Leadership with N4P Process". TSMC (Press release). 26 October 2021.
  25. ^ "TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node". WikiChip. 26 October 2021.
  26. ^ a b "TSMC Introduces N4X Process" (Press release). TSMC. 16 December 2021.
  27. ^ a b "The Future Is Now (blog post)". TSMC. 16 December 2021.
  28. ^ a b "TSMC Unveils N4X Node". AnandTech. 17 December 2021.
  29. ^ a b Smith, Ryan. "Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance". AnandTech. Retrieved 13 June 2022.
  30. ^ "IRDS international roadmap for devices and systems 2017 edition" (PDF). Archived from the original (PDF) on 25 October 2018.
  31. ^ a b c Jones, Scotten (29 April 2020), "Can TSMC Maintain Their Process Technology Lead", SemiWiki
  32. ^ "Samsung Foundry Update 2019". SemiWiki. 6 August 2019.
  33. ^ "Samsung 5 nm and 4 nm Update". WikiChip. 19 October 2019.
  34. ^ "5 nm lithography process". WikiChip.
  35. ^ a b Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". AnandTech. Retrieved 27 July 2021.
  36. ^ "TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node". WikiChip. 26 October 2021.
  37. ^ a b INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017, Section 4.5 Table MM-10 (p.12) entries : "SRAM bitcell area (um2)" ; "SRAM 111 bit cell area density - Mbits/mm2", archived from the original (PDF) on 25 October 2018, retrieved 24 October 2018
  38. ^ J.C. Liu; et al. A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application. 2020 IEEE International Electron Devices Meeting (IEDM). doi:10.1109/IEDM13553.2020.9372009.
  39. ^ Gartenberg, Chaim (29 July 2021). "The summer Intel fell behind". The Verge. Retrieved 22 December 2021.
  40. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Semiconductors.org. Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.
  41. ^ "5 nm lithography process". WikiChip. Retrieved 7 December 2017.
  42. ^ "Samsung 3 nm GAAFET Node Delayed to 2024".
  43. ^ Shilov, Anton. "Samsung: Deployment of 3nm GAE Node on Track for 2022". AnandTech. Retrieved 27 July 2021.
  44. ^ Shilov, Anton. "TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022". AnandTech. Retrieved 27 July 2021.
  45. ^ "15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". EE Times. 16 January 2017. Retrieved 4 June 2018.

External links[edit]

Preceded by
7 nm (FinFET)
MOSFET semiconductor device fabrication process Succeeded by
3 nm (FinFET/GAAFET)