Jump to content

ARM9

From Wikipedia, the free encyclopedia

This is an old revision of this page, as edited by 91.154.87.201 (talk) at 08:17, 19 November 2012 (→‎ARM9-based products: wlan, nas, etc; cleanup). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

ARM9 is an ARM architecture 32-bit RISC CPU family. With this design generation, ARM moved from a von Neumann architecture (Princeton architecture) to a Harvard architecture with separate instruction and data buses (and caches), significantly increasing its potential speed. Most silicon chips integrating these cores will package them as modified Harvard architecture chips, combining the two address buses on the other side of separated CPU caches and tightly coupled memories.

There are two subfamilies, implementing different ARM architecture versions.

Differences from ARM7 cores

Key improvements over ARM7 cores, enabled by spending more transistors, include[1]:

  • Decreased heat production and lower overheating risk.
  • Clock frequency improvements. Shifting from a three stage pipeline to a five stage one lets the clock speed be approximately doubled, on the same silicon fabrication process.
  • Cycle count improvements. Many unmodified ARM7 binaries were measured as taking about 30% fewer cycles to execute on ARM9 cores. Key improvements include
    • Faster loads and stores; many instructions now cost just one cycle. This is helped by both the modified Harvard architecture (reducing bus and cache contention) and the new pipeline stages.
    • Exposing pipeline interlocks, enabling compiler optimizations to reduce blockage between stages.

Additionally, some ARM9 cores incorporate "Enhanced DSP" instructions, such as a multiply-accumulate, to support more efficient implementations of digital signal processing algorithms.

Switching to a Harvard architecture entailed a non-unified cache, so that instruction fetches do not evict data (and vice versa). ARM9 cores have separate data and address bus signals, which chip designers use in various ways. In most cases they connect at least part of the address space in von Neumann style, used for both instructions and data, usually to an AHB interconnect connecting to a DRAM interface and an External Bus Interface usable with NOR flash memory. Such hybrids are no longer pure Harvard architecture processors.

ARM9TDMI-based cores

ARM9TDMI is a successor to the popular ARM7TDMI core, and is also based on the ARMv4T architecture. Cores based on it support both 32-bit ARM and 16-bit Thumb instruction sets and include:

  • ARM920T with 16 KB each of I/D cache and an MMU
  • ARM922T with 8 KB each of I/D cache and an MMU
  • ARM940T with cache and a Memory Protection Unit (MPU)

ARM9E-based cores

ARM9E, and its ARM9EJ sibling, implement the basic ARM9TDMI pipeline, but add support for the ARMv5TE architecture, which includes some DSP-esque instruction set extensions. In addition, the multiplier unit width has been doubled, halving the time required for most multiplication operations. They support 32-bit, 16-bit, and sometimes 8-bit instruction sets.

  • ARM926EJ-S with ARM Jazelle technology, which enables the direct execution of 8-bit Java bytecode in hardware, and an MMU
  • ARM946
  • ARM966
  • ARM968

ARM9-based chips

ARM9-based products

See also

References

  1. ^ "Performance of the ARM9TDMI and ARM9E-S cores compared to the ARM7TDMI core", Issue 1.0, dated 9 February 2000, ARM Ltd.
  2. ^ STR9 Website; STMicroelectronics.
  3. ^ [1]
  4. ^ VTech V.Flash product page from ARM
  5. ^ http://zyxel.nas-central.org/wiki/Category:NSA-310
  6. ^ http://zyxel.nas-central.org/wiki/Category:NSA-320
Retrieved from "https://en.wikipedia.org/w/index.php?title=ARM9&oldid=523813268"