Achronix

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Achronix
Private
Industry Semiconductors
Founded 2004
Headquarters San Jose, California, US
Key people

Robert Blake (CEO), John Lofton Holt (Chairman), Chris Pelosi (VP HW Engineering), Kamal Choudhary (Sr. VP SW Engineering), Raymond Nijssen (VP System Engineering), Randy Jurrat (VP of Operations), Steve Mensor (VP Marketing),

Steve Dodsworth (VP Sales),
Products FPGA
Number of employees
<200
Website www.achronix.com

Achronix Semiconductor is a fabless semiconductor company based in San Jose, California with R&D in Bangalore, Karnataka. It designs high-density and high-performance field-programmable gate arrays (FPGA) chips, manufactured at Intel Fabs since 2012. Its latest FPGA product family built on 22 nm is called Speedster 22i and is manufactured using Tri-Gate process.[1] Company was founded in 2004 by group from Cornell University: Dr. Rajit Manohar, Dr. Clinton Kelly IV, Dr. Virantha Ekanayake and John Lofton Holt.[2] It was included in EE Times 60 Emerging Startups list in 2005.[3] Prototypes of its FPGAs was made using 180 nm (TSMC, September 2005) and 90 nm (STMicroelectronix, April 2006).[2][4]

Achronix has raised over $120 million in venture funding.[5] According to interview in December 2012 with company chairman John Lofton Holt, Achronix may do IPO in 2014.[6]

Products[edit]

Early product line from Achronix was "Speedster" FPGAs manufactured using 65 nm node. This chip used 4-input LUTs, grouped in blocks of size 8 LUT each. Total available LUT count was 25 - 164 thousands, and chip had maximum frequency of 1.5 GHz.[7]

The Speedster22i family of FPGAs is their current product and is the industry’s first FPGAs with embedded hard IP for high-performance wireline applications. The hard IP includes 10/40/100G Ethernet, Interlaken, PCI Express Gen3 x8 and up to DDR3 x72 controllers. Hardening key interface IP in the Speedster22i devices frees up the programmable logic fabric that would otherwise need to be used to implement the interfaces using soft IP. The hard IP approach increases the effective capacity of the FPGA and significantly reduces the FPGA power consumption.


References[edit]

  1. ^ Dylan McGrath, Intel to fab FPGAs for startup Achronix // EETimes, 10/31/2010
  2. ^ a b The World's Fastest CMOS FPGA for Commercial and Extreme Environments // Achronix, 2005[dead link]
  3. ^ EE Times updates list of 60 emerging startups. Fourth edition of the Silicon60 // Peter Clarke, EETimes, 11/1/2005: "EE Times welcomes the following companies to the 60 Emerging Startups list version 4.0: Achronix Semiconductor LLC"
  4. ^ Reconfigurable, High Density, Gigahertz Speed Low Power Radiation Hardened FPGA Technology // Achronix, 2009, slide 9
  5. ^ Management -> John Lofton Holt // Achronix
  6. ^ Yoshida, Junko (2012-04-12). "Achronix 6 billion transistor FPGAs: Take two". EE Times. Retrieved 2016-05-11. 
  7. ^ Donald G. Bailey, Design for Embedded Image Processing on FPGAs, chapter: "2.4.4 Achronix"

External links[edit]

See also[edit]