|Designed by||Luke Leighton, Libre-SOC Team|
|Architecture and classification|
|Technology node||180 nm|
|Instruction set||Power ISA 3.0|
Libre-SOC is a libre soft processor core originally written by Luke Leighton and other contributors, announced at the OpenPOWER Summit NA 2020. It adheres to the Power ISA 3.0 instruction set and can be run on FPGA boards, currently booting MicroPython and other bare-metal applications.
The purpose of Libre-SOC is to be a system on a chip (SoC) with 3D and video capability built-in as part of the Power ISA, suitable for single-board computers, netbooks, IoT devices and other small form factors, while retaining a completely free and open design.
Libre-SOC is a 64-bit bi-endian scalar processor core, implementing a subset of the Power ISA 3.0 instruction set. It has 32× 64-bit general purpose registers. It uses Wishbone for the memory interface.
The Libre-SOC core will be a hybrid design, based around a precise-augmented version of the historic CDC 6600 microarchitecture, merging traditional general purpose, vector and graphics computing into a single execution unit reducing complexity and size of the complete chip as well as simplifying 3D driver development. This constitutes the need to add a small addition to the OpenPOWER instruction set architecture called "Simple-V". SVP64, currently in draft, extends OpenPOWER register files to 128, including CR fields, in order to cope with modern 3D and Video workloads, effectively making Libre-SOC a Vector processor.
Like Microwatt, the initial development was done in around three months, included the entire integer processing functionality of the instruction set; the bare minimum to make it compliant, with no memory management unit and no floating-point unit. Libre-SOC's rapid development is, like Microwatt, down to the significant use of software engineering practices including thousands of unit tests and by Microwatt source code as a reference design.
Libre-SOC is unusual in that it is designed using nMigen, a Python-based hardware description language (HDL). Also, to retain full transparency associated with "libre", the ASIC layout is performed with coriolis2, a VLSI toolchain developed and maintained by Sorbonne University's Laboratoire d'Informatique de Paris 6.
While Libre-SOC is as developed as a libre software project, eventually the goal is to produce real "hard" hardware products as opposed to the "soft" synthesised versions that reflects the actual development.
Libre-SOC began its life when Luke Leighton wanted there to be a completely free and libre system on a chip offering. He initially opted for a RISC-V base, but later switched to OpenPOWER when that seemed like a better fit for the project. It is the second processor written from scratch using the OpenPOWER ISA 3.0, and the first libre core that is completely independent of IBM.
- Libre-SOC's official page
- Libre-SOC source code
- OpenPOWER list of Libre/Open implementations of the POWER ISA
- Articles about Libre-SOC
- Williams, Chris (2019-08-29). "Get your royalty-free soft-core OpenPOWER processor core blueprints here. Extra, extra – read all about it". The Register.
- OpenPOWER Summit NA 2020: The LibreSOC Initiative: a hybrid CPU/VPU/GPU
- Libre-SOC Still Persevering To Be A Hybrid CPU/GPU That's 100% Open-Source
- 6600 scoreboard architecture
- XDC2020 Libre-SOC talk
- Simple-V Vectorisation for the OpenPOWER ISA
- The LibreSOC Project: Simple-V Vectorisation. Why we decided to invent a new Vector system on top of OpenPOWER
- SVP64 Draft Specification
- OpenPOWER ISA unit tests
- Libre-SOC git repository for GDS-II layout
- Libre-SOC 180nm Power ISA ASIC Submitted to Imec for Fabrication
- The Libre RISC-V Vulkan Accelerator Will Be Targeting 25 FPS @ 720p, 5~6 GFLOPs
- LibreSOC Still Striving To Produce An Open-Source Hybrid CPU/GPU Built On OpenPOWER
- The Libre-RISCV SoC
- NLNet Grants approved, Power ISA under consideration
- Libre-SOC 180nm ASIC plan