DEC J-11

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DEC J-11 microprocessor

The J-11 is a microprocessor chip set that implements the PDP-11 instruction set architecture (ISA) jointly developed by Digital Equipment Corporation and Harris Semiconductor. It was a high-end chip set designed to integrate the performance and features of the PDP-11/70 onto a handful of chips. It was used in the PDP-11/73, PDP-11/83 and Professional 380.

It consisted of a data path chip[1] and a control chip[2] in ceramic leadless packages mounted on a single ceramic hybrid DIP package. The control chip incorporated a control sequencer and a microcode ROM.[2] An optional separate floating-point acclerator (FPA) chip could be used, and was packaged in a standard DIP. The data path chip and control chip were fabricated by Harris in a CMOS process while the FPA was fabricated by Digital in their "ZMOS" NMOS process.

The design originally was intended to support multiple control chips to allow implementation of additional instructions such as the Commercial Instruction Set (CIS), but no such control chips were ever offered.


  1. ^ "J-11 Data Chip Specification" (PDF). Digital Equipment Corporation. July 1, 1982. 
  2. ^ a b "J-11 Control Chip Specification" (PDF). Digital Equipment Corporation. June 22, 1982.