LatticeMico32
| Designer | Lattice Semiconductor |
|---|---|
| Bits | 32 |
| Introduced | 2006 |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed 32-bit |
| Branching | Compare and branch |
| Endianness | Big |
| Extensions | User-defined |
| Open | Yes |
| Registers | |
| General-purpose | 32 |
LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs). It uses Harvard architecture.
LatticeMico32 is licensed under an open intellectual property (IP) core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host-architecture (FPGA, ASIC, virtual emulation.) Both the CPU-core and the developer-tool chain are available in source-code form, allowing third-parties to implement changes to the processor architecture.
Features
- RISC load/store architecture.
- 32-bit data path.
- 32-bit instructions.
- 32 general purpose registers.
- up to 32 external interrupts.
- Configurable instruction set including user defined instructions.
- Optional caches.
- Optional pipelined memories.
- Dual Wishbone memory interfaces.
- Memory mapped I/O.
- 6 stage pipeline.
Toolchain
- GCC - C/C++ compiler.
- Binutils - Assembler, linker and binary utilities.
- GDB - Debugger.
- Eclipse - IDE.
- Newlib - C library.
- uCos-II, uITRON, RTEMs - RTOS.
- uCLinux - O/S.