OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On March 21, 2006, Sun released the source code to the T1 IP core under the GNU General Public License v2. The full OpenSPARC T1 system consists of 8 cores, each one capable of executing four threads concurrently, for a total of 32 threads. Each core executes instruction in order and its logic is split among 6 pipeline stages.
On December 11, 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project. It was also released under the GNU General public license v2. OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.
- S1 Core (a derived single-core implementation)
- FeiTeng an implementation designed and produced in China for supercomputing applications
- SPARC (Scalable Processor ARChitecture)
- Field-programmable gate array
- "Sun Accelerates Grown of UltraSPARC CMT Eco System". Sun Microsystems. 2007-12-11. Retrieved 2008-05-23.
- "OpenSPARC Frequently Asked Questions". Oracle. Archived from the original on 2012-10-17. Retrieved 2021-03-20.