|Max. CPU clock rate||32 kHz to 320 MHz|
|Architecture and classification|
|Min. feature size||0.8 μm to 40 nm|
V850E2v2 (FIX ME),
|Instruction set||V800 Series|
v850e1: 80 (83)
V850e3v5: FIX ME
|Products, models, variants|
|Product code name(s)|
|Predecessor||"V80" CISC core|
V850 is the trademark name for a 32-bit RISC CPU architecture of Renesas Electronics for embedded microcontrollers, introduced in the early 1990s by NEC and still being developed as of 2018.
V850 Family has been evolved by many microarchitecture extensions until today, but all the extensions have binary code level backward compatibility of programs across a quarter century. Its basis is 32 of 32-bit general-purpose registers with load/store architecture. It has high code efficiency because most of frequently used instructions are mapped into 16-bit half-word.
In its earlier stage, it mainly focused on ultra-low power consumption such as 0.5 mW/MIPS. V850 has been widely used in variety of applications including: optical disk drives, hard disk drives, mobile phones, car audio and inverter compressors for air conditioners. But today, new microarchitectures are mainly toward high performance and high reliability with such as dual-lockstep redundant mechanism for automotive industry. Nowadays, V850 Family and RH850 Family are comprehensively used in a car.
- 1 Overview
- 2 Application systems
- 3 Trademark strategy
- 4 Architecture
- 5 List of the V800 Series CPU cores
- 6 SoC solutions
- 7 Strategic confusion
- 8 Target software solutions
- 9 Software development tools
- 10 Hardware development tools
- 10.1 ICE (In-circuit emulators)
- 10.2 Flash ROM programmers
- 10.3 Evaluation boards
- 11 See also
- 12 References and notes
- 13 External links
The V850 is the trademark name for a 32-bit RISC CPU architecture for embedded microcontrollers of Renesas Electronics Corporation. It was originally developed and manufactured by NEC Corporation in the early 1990s (copyright mark for the microcode on the package shows ©1991) as a branch of the V800 Series:97,PDF103 and still being evolved until today.
Many compilers and debuggers are available from various development tool vendors.
Real-time operating systems are provided by compiler vendors.
In-circuit emulators (ICE) are provided by many vendors. Legacy prove pod based type, the JTAG based the N-Wire interface with the N-trace type, and the Nexus interface with the Aurora Trace type, are available.
The first V850 CPU core was used for many DVD drives manufactured by NEC Corporation, then Sony Optiarc. NEC Electronics (currently Renesas Electronics) itself intensively developed application-specific standard products (ASSPs) for optical disk drives named SCOMBO® Series. This first generation of processor core was also used for hard disk drives manufactured by Quantum Corporation (see the photo).
The V850/xxn product line, started with V850/SA1 and V850/SV1 expanded its application to ultra-lo-power products such as "handy camcorders." It has main and sub internal oscillator amplifier working from 1.8 V to 3.6 V with external resonator, such as crystal and ceramic. Software STOP mode, which internal watch timer operates with 32.768 kHz sub-oscillator, consumes typically 8μA of electrical current only. NEC also launched V850/SB1 for car audio with IEBus controller in 1998, which is ultra-low power (3.6 mW@5 V/MIPS) and ultra-low noise (EMI/EMS) 5 V product. And V850/SC1 was also for "car audio". These strategical product line expansion well succeeded to enlarge the number of sold devices.
This first generation of V850 core is also used for some NEC's mobile phones. It is also used for the programmable host CPU of some small form factor "GSM/GPRS with GPS" embedded modem modules.
The V850E core targeted SoC as well as standard products, used for some Japanese domestic mobile phones, including Sony Mobile's and NEC's. V850E and V850ES are also used for air conditioning inverter compressors. At this stage, one of mass market was car audio. The V850ES core succeeded low power embedded product line, which is ISA compatible with V850E. NEC Electronics (currently, Renesas Electronics) adopt V850 CPU core for its "USB 3.0" controllers.:11
Around 2005, feasibility study for "FlexRay" controller on V850E platform had been started in several companies. Yokogawa Digital Computer (currently DTS INSIGHT) developed evaluation board named GT200; with a V850E/IA1 and a FPGA, which employs "FlexRay" controller developed by Bosch.:78,PDF80
Current V850 Family line up (including Renesas RH850 Family, based on V850E3 core, as of 2018) covers mainly automotive applications as well as "inter equipment connectivity" and "motor-control" specific MCUs. The V850 Family (based on V850E, V850ES, and V850E2 cores) and the RH850 Family (based on V850E3 core, as of 2018) are used in automotive industry comprehensively.
The V850 is a trademark but not a registered trademark. NEC once applied it to the Japan Patent Office, but it was rejected for registration, as it was a natural extension of the series number. But this action has enough effect to prevent some other people or organization registering it as the trademark. In addition Renesas (formerly NEC) has been using the V850X/xxn type trademark, such as V850E/MA1, for more than 20 years, because the combination of 1 alphabet with 2 numerical string can not be granted as the "registered" trademark. So, it is free to use without any registrations, and no one can blame it.
One exception is V850E/PHO3 (PHOENIX 3, or PHOENIX-FS).:3:33 Another usage of PHOENIX 3 of Renesas Electronics is the COOL PHOENIX 3, which employs ARM Cortex-M0 core. By the way, "PHOENIX 3®" is the registered trade mark name of The 3DO Company as USPTO Reg. 2,009,119.
According to the current Renesas Electronics' documentation, at least the following strings are insisted as its trademark. "V800 Series," "V850 Family," "V850/SA1," "V850/SB1," "V850/SB2," "V850/SF1," "V850/SV1," "V850E/MA1," "V850E/MA2," "V850E/IA1," "V850E/IA2," "V850E/MS1," "V850E/MS2," "V851," "V852," "V853," "V854," "V850," "V850E," and "V850ES."
Because the V850 trademark has been used for more than 20 years, most people does not know that the RH850 Family is based on an extension of the V850 instruction set architecture, and has backward compatibility with V850, V850E, V850ES, and V850E2. The RH850 is thought as a new face without huge legacy software assets of V850.
The basis of V810 and V850 is a typical general-purpose registers-based load/store architecture.:4 They have 32 of 32-bit general-purpose registers, and R0 is fixed as Zero Register which contains always zero. In V850, R30 is implicitly used by SLD/SST; 16-bit short format load/store instructions as element pointer (ep),which addressing mode comprises base address register ep and immediate operand offsets. In V850E or later microarchitectures, R3 is also implicitly used by PREPARE/DISPOSE; call stack frame creation and unwinding instructions, as stack pointer. Compilers' calling convention also uses R3 as the stack pointer.
Original V850 has simple 5-stage 1-clock pitch pipeline architecture.:114–126 These are the significant feature of RISC; reduced instruction set computers. But object code size is about the half of that of MIPS R3000.:5 The reason is V810 and V850 adopt 16-bit and 32-bit 2-way form length instruction format,:38–40:17:29–30 and the most of frequently used instructions are mapped into 16-bit half-word. In other words, 16-bit external bus width is relatively enough to provide instructions continuously without pipeline stalling, which enables low power consumption on the application board, and is suitable for mobile equipments. This concept is similar to Renesas (formerly, Hitachi) SH, ARM Thumb, and MIPS16 instruction set architectures.:4
In addition, implementing instruction set is cautiously selected. For example, function call with Jump and (Register) Link instruction,:61:20:64 which save next PC on a register (fixed to R31 in V810), is also one of RISC technique to reduce the number of instructions. Return from the function can be done by jmp [Rn] (jmp [R31] in V810) instruction.:61:23:65 Typical CISC processors use call & return instructions and push the next PC on their stack memory area.
But V810 and V850 have some microarchitecture differences. V810 adopts microprogram operation method for some instructions; floating-point arithmetic and bit string operations, while V850 is a hundred percent hardwired control method. As the result, for example, the first V850 does not have floating-point arithmetic and bit manipulation instruction sets; including the "find first one/zero" (search 1/0; SCH1x/SCH0x), except for "set/clr/negate a bit" (SET1/CLR1/NOT1). Those extended instruction sets are revived in V850E2x extensions.
Though V800 Series adopt RISC instruction set architecture, their assembly language is hand-coding friendly. They adopt straight forward load/store architecture.:4 In addition, the "interlock" mechanism both for the data hazards and for the branch hazards are implemented,:33–35 in other words, assembly language programmer does not need to consider any delay slots. 32 general-purpose registers provide flexibility for assembly language users. Mixture of hand-assembled codes and C language compiled codes is available by using compiler options, such as "-mno-app-regs" in Gnu Compiler Collection.
Main purpose of the modification from V810 to V850 is saturation arithmetic for customers' request.
V850 Series repeated many microarchitecture extension, but all the extensions have backward compatibility. In other words, all the old binary software assets, including written in a quarter century ago, work on every new core. In addition, each microarchitecture has circuit implementation variants and fabrication process technology variants across a quarter century.
The first generation of V850 does not have unsigned load instructions, which was removed from V810 (as IN.H and IN.B), then it was added again as LD.HU and LD.BU in the second generation; V850E (V850E1) Series. In addition, V850E has some other user-friendly CISCy extensions such as "call table," "switch," and "prepare/dispose".:217
In 2001, NEC launched V850ES core, which is ultra-low-power series, but is ISA compatible with V850E.
In 2009, NEC Electronics introduced V850E2M as dual-core with 2.56MIPS/MHz and 1.5 mW/MIPS.
In 2011, Renesas disclosed SIMD extension for V850 as V850E2H. As for SIMD extension, some academic studies were done. But architectural documentation for this latest product line is disclosed to automotive customers only. It can not be found on Renesas' web site. Its name seems to be changed to V850E3 or G3H. The only way to know about its instruction set is to do "reverse engineering" from the GNU Compiler Collection.
The original V810 and V850 CPU architecture is designed for ultra-low power applications.
The V810 operates at from 2.2 V to 5.5 V with 5 V 0.8 μm (CZ4) fabrication process, which power dissipation with Dhrystone MIPS are 500 mW with 15MIPS and 40 mW with 6 MIPS at 5 V and 2.2 V, respectively. It is one of the most low power 32-bit microcontroller product in the early 1990s. This specification can be achieved both by well considered instruction set architecture and by precisely tuned 5-stage 1-clock pitch pipeline microarchitecture, both of them are the benefit of the simplified RISC feature.
This ultra-low power DNA is succeeded by V850/Sxn product line, those are still alive in mass production over 20+ years. Most of them are produced with 3.3 V with 0.35μm (UC1) fabrication process, which CPU core is precisely tuned to operate from 1.8 V to 3.6 V, working at 32.768 kHz (sub-osc.) to 16.78 MHz (main-osc.) with internal oscillator amplifier plus external resonator (crystal or ceramic).
Its power dissipation is 2.7 mW/MIPS for 3.3 V 0.35 μm (UC1) fabrication process, and 3.6 mW/MIPS for 5 V 0.35 μm (CZ6) fabrication process. "Software STOP" stand-by mode for mask ROM version of V850/SA1, which internal watch timer operates at 3.3 V with 32.768 kHz sub-oscillator (IDD6), consumes typically 8 μA electrical current only. And, Subclock normal operation mode at 3.3 V with 32.768 kHz consumes 40 μA typically, 140 μA at the maximum. (IDD5):440,IDD5
Its 1.8 V typical CPU operation current at 32.768 kHz might be 22 μA (40 μA ÷ 3.3 V × 1.8 V), which power dissipation should become 40 μW. It corresponds to 1.0 mW/MIPS (40 μW ÷ 0.032768 MHz ÷ 1.15 DMIPS/MHz ÷ 1000).
The V850/Sxn product line is also tuned for low noise both with EMI and with EMS. Especially, V850/SB1 and SB2 are specially tuned for low EMI noise with 5 V internal voltage regulator, which enables high sensitivity of receiving RF for car radio.:41–44
In 2011, NEC launched 3rd generation microarchitecture V850ES ultra-low-power series, which insists 1.43 mW/MIPS at operating voltage range from 2.2 V to 2.7 V, but this first implementation of V850ES microarchitecture seems to be incomplete compared with later generations of the same architecture. Its "Sub-IDLE" stand-by mode for mask ROM version of V850ES/SA2 and V850ES/SA3, those internal RTC operate at 2.5 V with 32.768 kHz sub-oscillator (IDD6), consume typically 5 μA electrical current only. But, Subclock normal operation mode at 2.5 V with 32.768 kHz consume 40 μA typically, 100 μA at the maximum.:509 Its 2.2 V typical CPU operation current at 32.768 kHz might be 31 μA (40 μA ÷ 2.5 V × 2.2 V), which power dissipation should be 68 μW. It is about 1.7 times of V850/SA1. It corresponds to 1.6 mW/MIPS (68 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000).
The V850ES/JG3-L product line has ultra-low power variants, named μPD70F3792, 793 and μPD70F3841, 842. They can operate from 2.0 V to 3.6 V with 18 μA typical electrical current at 32.768 kHz,:1002, 1041 which should be 22 μW at 2.0 V (18 μA × 2.0 V ÷ 3.3 V × 2.0 V). It corresponds to 0.52 mW/MIPS (22 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000). In addition, their sub-clock idle mode, with watch timer, power consumption should be typically 3.4 μW at 1.8 V (3.5 μA ÷ 3.3 V × 1.8 V × 1.8 V).:1002, 1041
The power consumption of NA85E2 (V850E2) core is much larger compared with NU85E (V850E1) core in the same CB-12L (UX4L) fabrication process. The reason is that V850E2x core has 128-bit width instruction prefetch bus and plural of Instruction Prefetch Queues,:16 while average instruction length of V800 Series is almost 16-bit.:17 It means 16 instructions are possibly fetched from the memory at once, then the memory and the prefetcher circuits sleep rest 3 to 7 cycles for dual-pipeline superscalar architecture. This gap enlarges electrical current amplitude differences. In addition, the peak electric current exceeds allowance for the voltage stabilizers of mobile gadgets. As for V850E2M CPU core, it is publicly introduced as 1.5 mW/MIPS, 3 times of former generations, although it should have advantages of new fabrication process technologies. Some mobile equipment avoids using dual-instruction execution (dual-pipeline superscalar), in other words, adopting the single-instruction (single-pipeline) execution setting to reduce electrical current amplitude differences.
Because the V850 Family:16 is developed as a branch of V800 Series,:97,PDF103 the basic CPU architecture is inherited from V810. Instruction set architecture of the first V850 is drastically modified from that of V810, but the difference is within a patch level from GNU Compiler Collection point of view. The main purpose of this change is to implement saturation arithmetic by customers' request.
Detailed design methodology of V810 is described in a journal. V850 utilizes this design assets. But datapath logic was changed from dynamic logic to static logic, to enable 32.768 kHz real-time clock frequency operation mode.
The register-transfer level "CPU architecture design" of the V810 is developed with the Functional Description Language (FDL) on the Falcon Simulator software, those are NEC's in-house CAD tools. This methodology is the same as that of NEC V60. In the late 1980s, the Verilog HDL has not acquired by Cadence Design Systems yet. The FDL had been used until the middle of the 2000s, and was also used for the development of NEC's super-computer; named Earth Simulator.
The difference from V60 is that the circuit diagram was written with schematic editor, not of Calma, but of Mentor Graphics called NETED, a part of the Design Architect product on Apollo Computer's workstation, which is the most major schematic editor at that moment. It enabled to generate netlists, such as EDIF and SPICE, for LVS program like cadence's Dracula products, and NEC's in-house and Zycad netlist for logic simulation. Later on, this circuit diagram of NETED became able to generate gate-level Verilog HDL netlist for V850.
Most of the register-transfer level FDL netlist was translated to the gate-level schematic by hand, because the logic synthesis has not yet to be practical use at that moment. The FDL was divided into datapath and random logic precisely. For the datapath part, the gate-level circuit diagram enabled manually repeated artwork. On the other hand, for the random logic part, logic synthesis was tried to use for generating gate-level schematic, but it was about 10% of the total circuit.
In addition, formal verification has also not to be practical use yet, which means full regression test by dyamic logic simulation is required for gate-level netlist to compare with RTL one. For gate-level logic simulation, NEC's in-house CAD tool named V-SIM is usually used. But sometimes hardware emulator, such as Zycad LE simulation accelerator, is used for this purpose. (Refer to:.:13 In this material, the performance of Zycad LE is compared with NEC's HAL, but initial design decade differs.)
Instruction opcode table
- 1st map opcodes
- All the opcode (operation code) of the hardwired control operation is closed within the first 16-bit half-word, more precisely, the first 7 bits from MSB. A 64-word depth ROM structure with branch condition code table is enough for decoding hardware. If a 16-bit literal operand is required, it is located in the second half-word. Microprogram control operations; bit strings and floating-point arithmetic instructions, are also located in the second 16-bit half-word. As the result, all the instructions become 16-bit and 32-bit 2 way form length. Unsigned load form memory mapped I/O is implemented as In instruction. Arithmetic and logical instructions are not fully but relatively orthogonal.
- V810 does not have saturation arithmetic instructions, but 1 additional instruction in format II, such as SAT which checks flags (Overflow, Sign, Zero, and Half-word) and rewrites specified register, might be enough both for signed and unsigned, and for word and half-word, arithmetic operations.
000 001 010 011 100 101 110 111 Format 000 X MOV ADD SUB CMP SHL SHR JMP SAR I(R,r) 001 X MUL DIV MULU DIVU OR AND XOR NOT 010 X MOV ADD SETF CMP SHL SHR SAR II(imm5,r) 011 X TRAP RETI HALT LDSR STSR Bit str.
Bcond III(disp9) BV BZ/BE BN(BS) BLT BNV BNZ/BNE BP(BNS) BGE BC/BL BNH BR BLE BNC/BNL BH NOP BGT 101 X MOVEA ADDI JR JAL ORI ANDI XORI MOVHI IV/V 110 X LD.B LD.H LD.W ST.B ST.H ST.W VI(disp16[R],r) 111 X IN.B IN.H CAXI IN.W OUT.B OUT.H Float OUT.W VI/VII
- "NOP" is an alias of "Non-BR".
V850 (1st Gen.)
- 1st map opcodes
000 001 010 011 100 101 110 111 Format 000 MOV NOT DIVH JMP SATSUBR SATSUB SATADD MULH I(R,r) 001 OR XOR AND TST SUBR SUB ADD CMP 010 MOV SATADD ADD CMP SHR SAR SHL MULH II(imm5,r) 011 SLD.B SST.B IV(disp7[ep],r) 100 SLD.H SST.H IV(disp8[ep],r) 101 Bit SLD.W / SST.W Bit[3:0] Bcond IV/III 110 ADDI MOVEA MOVHI SATSUBI ORI XORI ANDI MULHI VI(disp16[R],r) 111 LD.B 2nd Map ST.B 2nd Map JARL Bit[15:14]
- "NOP" is an alias of "MOV R0,R0".
- 2nd map opcodes
000 001 010 011 100 101 110 111 Format  1st Map Bit[10:5]=111001 0 LD.H VII 1 ST.H VII  1st Map Bit[10:5]=111011 0 LD.W VII 1 ST.W VII [26:24] 1st Map Bit[10:5]=111111 000 SETF LDSR STSR undef SHR SAR SHL undef IX(R,r) 001 TRAP HALT RETI 1st Map
Illegal instruction X 01X Illegal instruction — 1XX Illegal instruction —
- 1st map opcodes
000 001 010 011 100 101 110 111 Format 000 —† NOT SWITCH JMP ZXB SXB ZXH SXH I(R,r0) MOV DBTRAP Bit
SATSUBR SATSUB SATADD MULH I(R0,r31) / IV undef I(R0,r) / IV DIVH I(R,r) / IV 001 OR XOR AND TST SUBR SUB ADD CMP I(R,r) 010 CALLT ADD CMP SHR SAR SHL undef II(imm5,r0) MOV SATADD MULH II(imm5,r) 011 SLD.B SST.B IV(disp7[ep],r) 100 SLD.H SST.H IV(disp8[ep],r) 101 Bit SLD.W / SST.W Bit[3:0] Bcond IV/III(disp9) 110 ADDI Bit[15:11]
ORI XORI ANDI Bit[15:11]
MOVEA MOVHI STASUBI MULHI 111 LD.B 2nd Map ST.B 2nd Map Bit[15:14]
2nd Map VII(disp16[R],r)
- †:"NOP" is an alias of "MOV R0,R0".
- 2nd map opcodes
000 001 010 011 100 101 110 111 Format 1st Map Bit[10:5]=111001 0 XXX LD.H VII(disp16[R],r) 1 XXX ST.H 1st Map Bit[10:5]=111011 0 XXX LD.W VII(disp16[R],r) 1 XXX ST.W 1st Map Bit[10:5]=11110X 0 XXX 1st Map Bit[15:11] JR(r=0) / JARL (r≠0) V(disp22) 1 XXX 1st Map Bit[15:11] PREPARE(r=0) / LD.BU XIII/VII(disp16[R],r) 1st Map Bit[10:5]=111111 0 000 SETF LDSR STSR undef SHR SAR SHL Bit[18:17]
0 001 TRAP HALT Bit[18:17]
undef X 0 010 SASF Bit
0 011 CMOV(imm5,r,w) CMOV(R,r,w) Bit[18:17]
undef Illegal instruction XI(c,R,r,w)
0 10X Illegal instruction 1 XXX LD.HU VII(disp16[R],r)
List of the V800 Series CPU cores
|CPU core||Product variants||GCC targeting options||Remarks|
|Revert patch required.
Available on Planet Virtual Boy.
GCC named gccVB.
Unsigned & signed load.
μcoded float (single)
6.7 mW/MIPS (5 V Product)
(V830 — V832)
High end products.
|V850 Family started
V851 — V852
|none or -mv850||Obsoleted products.|
4.4 mW/MIPS (5 V product)
|none or -mv850||Not for new developments.|
1.15 Dhrystone MIPS/MHz
Ultra-low power products.
3.6 mW/MIPS (5 V product)
2.7 mW/MIPS (3.3V product)
1.0 mW/MIPS (1.8 V Sub-ope.)
|-mv850e||Not for new developments.|
Unsigned & signed load.
1.3 Dhrystone MIPS/MHz
NB85E SoC core
NU85E SoC core
(Sony's & NEC's best-cellular.)
|-mv850e1 or ‑mv850es||Unsigned & signed load.|
N-Wire and N-Trace.
|-mv850es or ‑mv850e1||Unsigned & signed load.|
Ultra-low power products.
1.43 mW/MIPS (2.5 V product)
0.52 mW/MIPS (2.0 V Sub-ope.)
Shift to V850E2S requested.
|Patch required (maybe).||H/W float (single precision).|
NA85E2 SoC core
(NEC's long-running cellular.
Sets life = 2004—2012.)
|-mv850e2||Not for new developments.|
Many errata but still alive.
Single insn. executing.
(e.g. FIX ME)
NB85E2 SoC core
|-mv850e2||Errata cleaned up.|
Dual instruction executing.
|-mv850e2v3 and -msoft-float||S/W float.|
Dual instruction executing.
2.56 Dhrystone MIPS/MHz
Multi CPU core support.
|-mv850e2v3||H/W float (double precision).|
Dual instruction executing.
2.56 Dhrystone MIPS/MHz
Multi CPU core support.
|-mv850e2v3 and ‑msoft‑float||S/W float.|
1.9 Dhrystone MIPS/MHz
Multi CPU core support.
V850ES/xxn pin compat.
Shift to RH850 requested.
|-mv850e2v4 and ‑mloop
-mv850e3v5 and ‑mloop
64-bit multiple load/store.
H/W float (double precision).
Multi CPU core support.
SoC IP cores
In 1998, NEC started to provide V850 Family as an ASIC core to expand its ASIC business.
In addition, both the V850E1 CPU core named Nx85E
and the V850E2 CPU core named Nx85E2,
respectively, are also used for expanding its standard products business with ASIC design methodology.
Various SoC utilize this core. For example, in 2003, Dotcast, Inc. used NU85E core for a set top box receiver of the digital datacasting based on dNTSC (data in NTSC video) method. This core is fabricated with CB-10 0.25μm process technology which adopts 5 layered metal.:9–10
The NA85E2C core, which is developed in 1.5 V 150 nm CB-12L (UX4L) fabrication process, has many errata (4 pages appendix in preliminary architecture manual,:230–233 plus 7 pages another restrictions document, as long as disclosed on the web). But it seems not to be a matter for uses, because this is long-running product.
|NA851C||V851||CB-9VX||3.3 V||350 nm||UC1||33||With peripheral|||
|NA853C||V853||CB-9VX||3.3 V||350 nm||UC1||33||With peripheral|||
|NA85E||V850E1||CB-9VX||3.3 V||350 nm||UC1||Bulk core|||
|NB85E||V850E1||CB-9VX||3.3 V||350 nm||UC1||66||Bulk core|||||
|NB85ET||V850E1||CB-9VX||3.3 V||350 nm||UC1||66||w/ Trace I/F|||||
|NB85E||V850E1||CB-10||2.5 V||250 nm||UC2||66||Bulk core|||||
|NB85ET||V850E1||CB-10||2.5 V||250 nm||UC2||66||w/ Trace I/F|||||
|NU85EA||V850E1||CB-10VX||2.5 V||250 nm||UC2||100||Bulk core|||||
|NU85ET||V850E1||CB-10VX||2.5 V||250 nm||UC2||100||w/ Trace I/F|||||
|NDU85ETV14||V850E1||CB-12L||1.5 V||150 nm/
|UX4L||w/ Trace I/F|||||
|NDU85ETVxx||V850E1||CB-12M||1.5 V||150 nm/
|UX4M||w/ Trace I/F|||||
|NA85E2C||V850E2||CB-12L||1.5 V||150 nm/
|UX4L||200||w/ Trace I/F|||||
|NB85E2C||V850E2||CB-12L||1.5 V||150 nm/
|UX4L||200||w/ Trace I/F|||||
|V850E2x||CB-130L||1.2 V||130 nm/
|—||—||CB-90L||1.2 V||90 nm/
||UX6L||Replaced by ARM946.|
|In-house||V850E2x||UX6LF||1.2 V||90 nm/
||UX6LF||Renesas internal use only ???|
|—||—||CB-65L||1.2 V||65 nm/
Replaced by ARM1156.
|—||—||CB-55L||1.2 V||55 nm/
Replaced by ARM Cortex-M3.
|—||—||CB-40L||1.1 V||40 nm/
|UX8L||Replaced by ARM Cortex-M4.|
|In-house||V850E3||RV40F||1.1 V||40 nm/
|RV40F||320||Renesas internal use only ???|
FPGA prototyping systems for SoC
FPGA prototyping systems for V850E1, V850E2, and V850E2M core based SoC were intensively developed to expand SoC business. They comprised a V850 CPU core LSI (TEG†) board and "FPGA add-on"s. Most of SoC products were for mobile equipments; because the power dissipation of original V800-Series RISC architecture was much lower compared with CISC. It is the same logic as the ARM (which stands for Acorn RISC Machine) architecture is widely used for mobile gadgets.
†TEG: Test Element Group
- Renesas (NEC): Microssp (2006)
- Renesas (NEC): Hybrid Emulator (2007)
- Renesas (NEC): PFESiP® EP1 Evaluation Board (2008)
- Renesas (NEC): PFESiP® EP1 Evaluation Board Lite (2008)
- Renesas (NEC): PFESiP® EP3 Evaluation Board (2010): V850E2M CPU core, max. 266 MHz operation
Around 2011–2014, Renesas Electronics expanded the V850E2 product line intensively, but this high-pace expansion brought much confusions. For example, some of V850E2/xxn products have already been requested to replace with RH850/xnx as of 2018. It may be, or may not be, the Product Longevity Program (PLP) point of view.
In addition, in 2012 Renesas intensively started to promote the migration from 10 years old V850ES/Jx3 product lines to newly produced V850E2/Jx4, such as for Ethernet and for USB, but the newer products are not listed on their web site as of 2018.
Currently, Renesas Electronics is designing "dual" lockstep system, but its predecessor NEC V60-V80 had "multiple modular" lockstep mechanism called FRM either with roll-back by "retry" or with roll-forward by "exception" for each fault detected instruction in more than 20 years ago. In addition, NEC V60-V80 has plural of implementation of UNIX System V port product releases, one of which is real-time UNIX RX/UX-832 (here, 832 stands for μPD70833 (V80), not V832). Its multiprocessor implementation is called MUSTARD (A Multiprocessor Unix for Embedded Real-Time Systems), which works 8 processors at the maximum simultaneously, and their lockstep mechanism was dynamically configurable. Now, where are these technologies ?
Metrowerks once developed CodeWarrior compiler for V850, which was one of the major compiler provider of V850 in 2006. But around 2010, they discontinued it after absorption by Motorola's semiconductor sector in 1999, Freescale Semiconductor in 2003, currently NXP Semiconductors from 2015.
In 2006, NEC did not show any roadmap for the V850 Family as SoC cores. The V850E2 core, developed in 2004, described as if the last core for SoC. Instead of that, NEC introduced ARM9 (arm v5) and ARM11 (arm v6), especially for mobile equipments. But this corporate decision suddenly decreased both the net profit of LSI devices, because of the royalty for ARM and of the price competition with other ARM SoC providers. The sales revenue of the "V850 total solutions," such as development tools, real-time OS, middle-ware packages, and in-circuit emulators, also decreased. The number of sold V850 device count was also suddenly decreased because mobile equipments were the major customers of V850E1 and V850E2 cores at that moment. In 2009, NEC Electronics merged with Renesas Technology Corp.
In 2008, KMC (Kyoto Mictocomputer), which is one of the major and of the first provider of in-circuit emulator for V850 Family, announced exeGCC updating from Rel. 3 to Rel. 4, but it excluded V850 form this updating list, although PowerPC and ARM v7 was newly added. It chose SH-4A and ARM v7 instead of V850 and RH850 though it had been tightly worked with NEC and Renesas Electronics.
The V850 CPU cores run uClinux, but on October 9, 2008, Linux kernel support for V850 was removed in revision 2.6.27., because NEC stopped the maintenance. The person in charge of V850 Linux kernel maintenance was moved from NEC to Renesas by its merger, but his job was still compiler design and never returned to Linux kernel maintenance. This corporate decision prevent the porting possibility for Android. Regarding the Linux kernel support as of 2018, Renesas Electronics mainly focuses on SH3/SH4 and M32R processors. 
Target software solutions
- C runtime startup routine (crt0.S) for the latest v850e3v5 microarchitecture is available.
- Micro Digital Inc.: GoFast® for NEC V85x Fast Software Floating Point Library
- The GNU Compiler Collection: Software floating point
- The GNU Compiler Collection: Decimal floating point (libdecnumber.a)
Some of operating systems require the Memory Protection Unit (MPU) to divide tasks (or threads) strictly for reliability and safety reasons. In such cases, v850e2v3 (Gen. 3) microarchitecture or above are required.
ITRON based real-time OS
ITRON is an open standard specification of real-time OS (RTOS), which is major in Japan. Its specification is defined under leadership of Ken Sakamura as a part of TRON project. Initial letter I stands for "Industrial." Because ITRON specification defines interface and skeleton only, each vendor has its own taste of implementation.
- Toppers Project: Open source TOPPERS/JSP
- A.I. Corporation: Toppers-Pro/xxx
- T-Engine Project: Open source T-Kernel by TRON Forum
- eSOL: eT-Kernel; Extended T-Kernel — RTOS for embedded systems
- eT-Kernel/Compact, eT-Kernel/Embedded, eT-Kernel/POSIX
- eT-Kernel Multi-Core Edition
- eCos: Open source real-time operating system
AUTOSAR, OSEK/VDX compliant real-time OS
AUTOSAR is an open systems architecture of operating system for automotive industry. Its purpose is to establish the standardization of ECU; Electronic Control Unit for automotive engines. AUTOSAR is upper compatible specification of OSEK/VDX, which is also a consortium name of Germany established in 1993.
In Japan, this research was started in 2006 as a joint project by JAIST and DENSO. Renesas Electronics joined this project in 2009. Because current RH850 and V850 is mainly targeted for automotive industry, it is one of a strategical product of Renesas Electronics. But documentation is only in Japanese probably because its main customer is Toyota Motor Corporation.
- Renesas: RV850 (documents are in Japanese only)
- ETAS GmbH: RTA-OS RH850/GHS, RTA-OSEK V850E/GHS
- Mentor Graphics (formerly Accelerated Technology, Inc.): Nucleus OSEK
- HighTec EDV-Systeme GmbH: EB tresos Safety OS
- Toppers Project: Open source TOPPERS/AUTOSAR
- eSOL: eMCOS AUTOSAR profile
Other real-time OS
- Wind River Systems:
- On October 9th 2008, Linux kernel support for V850 was removed in revision 2.6.27, preventing the possibility of porting Android.
- Renesas: SD Memory Card Control
Software development tools
Compilers and assemblers
Compilers for the V850 Fmily and the RH850 Family include:
- The GNU Compiler Collection (the name is still v850 for RH850) developed both:
- C Compiler Package for V850 Family
- CA850 C compiler for V850E1 and V850ES (v850e1 and/or v850es, a.k.a. Gen. 1)
- CX C compiler for V850E2M and V850E2S (v850e2v3, a.k.a. Gen. 3)
- Software Package for V850 [SP850] for V850E2 (v850e2(v2), a.k.a. Gen. 2)
- CC-RH C compiler package for G3, G3K(H), G3M(H)
- C Compiler Package for V850 Family
Usually, dis-assemblers are provided as a part of C compiler or assembler packages.
- The GNU Binutils: objdump (v850-elf-objdump or v850-elf32-objdump)
- Radare2: Radare2 is a set of command-line programming tools for reverse engineering. Open-source code is available from GitHub repository.
- IDA Pro: IDA Pro is a freeware disassembler for hobby use. A plugin for V850 is available. Download site is gray for securities.
GUI based debuggers
- ID850: For the combination of CA850 compiler and SM850 instruction set simulator.
- ID850NW: For the combination of N-Wire based in-circuit emulators.
- ID850QB: For the combination of probing-pod based emulator IEQUBE2
- NDK (Naito Densei Kogyo Co. Ltd, Group): Operation started in 1950 as subsidiary of NEC.
- GHS (Green Hills Software): Multi: General-purpose debugger.
- Red Hat, Inc.: Insight (GDB-Tk): GUI front-end tightly combined with GNU Debugger.
- Mentor Graphics (formerly Accelerated Technology, Inc.): code|lab Developer Suite
- By N-Wire based in-circuit emulator vendors:
Instruction set simulators
- Renesas: SM850
- Open Virtual Platform: Instruction set simulator
- Synopsys: VDK for Renesas RH850 MCU
Automated code reviewers
Automated code reviewer, in other words, source code analyzer qualify the level of completeness of written software source code. This method is classified as dynamic code analysis and static code analysis.
Dynamic code analyzers with simulators
- Renesas: TW850
- TW850 Performance Analysis Tuning Tool is a general utility to improve effectiveness of software.
- Renesas: AZ850
- AZ850 System Performance Analyzer is a utility for RX850 real-time operating system to evaluate effectiveness of application programs.
- Gaio Technology: Coverage Master winAMS
Static code analyzers
- GHS (Green Hills Software): DoubleCheck ISA (Integrated Static Analysis) tool
- Rogue Wave Software, Inc: Klocwork
IDE (Integrated Development Environments)
IDE, Integrated Development Environment, is a framework to provide software development functions.
- Renesas: CS+ (formerly CubeSuite+)
- GHS (Green Hills Software): Multi
- Eclipse Plugins
Hardware development tools
ICE (In-circuit emulators)
Most of in-circuit emulators, such as Rnesas IE850 (formerly IECUBE2) , can be used both for V850 Family and for RH850 Family, but may require firmware updating. The latest "trace function" of the JTAG (N-Wire ) based in-circuit emulator is replaced from the N-Trace (single-ended signaling) to the Aurora Trace (differential signaling).
Full probing pod type
Full probing pod type in-circuit emulator is sometimes called as full ICE or legacy ICE.
- Renesas IE850 (formerly IECUBE2)
- Naito Densei Machida Mfg. Co., Ltd. (Operation started as NEC's subsidiary.)
- Asmis brand for custom LSIs.
ROM emulator type
- Lauterbach: ROM Monitor for V850:5
- KMC (Kyoto Microcomputer Co., Ltd.): PARTNER-ET II (obsoleted)
JTAG N-Wire and N-Trace type
N-Wire and N-Trace is a JTAG-based debugging interface specification, which circuit implementation is called TAP Controller (Test Access Port controller), primarily compiled by Philips N.V. (currently NXP Semiconductors) about a quarter century ago. But it is perhaps not disclosed publicly in its earlier stage. As the result, each semiconductor and in-circuit emulator vendor implemented similar interfaces independently. Nowadays, it is standardized by IEEE 1149.1 Working Group.
- Naito Densei Machida Mfg. Co., Ltd. (Operation started as NEC's subsidiary.): Asmis brand.
- Midas Lab.: RTE-2000H with PARTNER debugger
- Lauterbach: Trace32
- IAR Systems
- DTS INSIGHT (formerly YDC; Yokogawa Digital Computer): adviceLUNA II
- Computex: PALMiCE3 V850
- Sohwa & Sophia Technologies: Universal Probe Blue with WATCHPOINT debugger
- KMC (Kyoto Microcomputer Co., Ltd.): PARTNER-Jet (obsoleted)
Nexus and Aurora trace type
Nexus or IEEE-ISTO 5001-2003 is a standard debugging interface for embedded systems.
Aurora is a high speed signal transfer specification. Its data link layer communications protocol is a point-to-point serial links, and physical layer is a high speed differential signaling.
Flash ROM programmers
Because V850 Family is developed as a single chip microcontroller, every product integrates non-volatile memory. In its first stage, it was one-time programmable or UV EPROM type, but V853, V850/xxn Series and later, it becomes flash memory type.
Gang writers (gang programmers)
A gang writer, or a gang programmer, is an old terminology for programmable ROM writers, or programmers. Its name origin comes from that it steals the binary code from one device, and write it to plural ones simultaneously. This read device is sometimes called as a master device. For mass production use, a dedicated attachment board with "a set of sockets," i.e. "a gang," is needed. As usual, instead of a programmed master device, an object code file can be copied from a PC via download cable, or from a USB stick. Most of gang writers accept ASCII format files such as Intel HEX and Motorola SREC, or binary format files such as ELF.
This method is suitable for mass production.
- TESSERA Technology Inc.: Stick GANG Writer
Programming service providers
Flash ROM programming service providers exit in most of countries.
- Minato Holdings, Inc.
- Minato Holdings, Inc. (in Japanese) is a Japanese company started as an automated test equipment vendor for memory LSIs. Nowadays, it provides flash ROM programming service for various devices, including V850 and RH850, with its own made gang writers and full automatic device handler machines.
On board programming with ICE
Most of JTAG-based in-circuit emulators have an on board flash ROM programming function via debug port.
May be or may not be IEEE standard 1532-2002; a standard for in-system configuration of programmable components.
Direct connection via RS-232C
If the target board has a RS-232C connector and a transceiver (driver/receiver) IC, such as ICL32xx, for the UARTx peripheral function of V850 device, flash ROM programming with directly connected PC might be available (depends on devices:16–24 ). The Renesas Flash Programmer software V2 or V3 is required.
Dedicated on board programmer
On board programming is also available via UARTx or CSIx+HS peripheral on V850 devices by using dedicated programmer hardware (depends on devices:16–24).
- Renesas: PG-FP6
Ancient PROM writers
- Renesas PG-1500 (obsoleted)
- Renesas PG-1500 is a programmable ROM writer compatible with 27C1001A devices, UV EPROM or OTP; one-time PROM. This writer reads silicon signature from each device before programming by asserting 12.5 V to A9 (address #9) terminal. It must NOT be used for modern flash ROM burning.
Gray zone tools
Some gray zone hacking tools exit for V850 on car dashboards.
- VVDI PROG.:
References and notes
Harigai, Hisao; Kusuda, Masaori; Kojima, Shingo; Moriyama, Masatoshi; Ienaga, Takashi; Yano, Yoichi (1992-10-22). "低消費電力・低電圧動作の32ビットマイクロプロセッサV810" [A low power consumption and low voltage operation 32-bit RISC Microprocessor] (PDF). SIG Technical Reports, Information Processing Society of Japan. 1992 (82 (1992-ARC-096)): 41–48.
An advanced 32-bit RISC microprocessor for embedded control; V810 is introduced in this paper. The V810 has high performance and application specified functions. V810 dissipates less power than any other RISC chips. The V810 is the first 32-bit RISC microprocessor that operates at 2.2 V.
The V810 chip is fabricated by using 0.8 μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7 mm2 die.
- "NEC : Shareholder Information". www.nec.com.
- NEC (April 1999). "SEMICONDUCTORS SELECTION GUIDE" (PDF) (17th ed.).
- "CA830, CA850 C COMPILER PACKAGES" (PDF). NEC.
- Wang, Bobby (2010-08-04). "V850 Architecture Overview, High performance and Energy Efficient" (PDF). Renesas Electronics Corporation.
- "NEC ND-3530A firmware update like ND-3520A or ND-3540A". Club Myce - Knowledge is Power. 2010-09-04. Retrieved 2018-01-29.
"Optiarc AD7240S". www.cdrinfo.com. Team CDRInfo.COM. 2009-06-29.
Built-in CPU functionality
• Onboard 32-bit RISC CPU (V850ES core)
• Built-in RAM (14KB)
• Power management functionality
• Built-in peripheral circuits (timer, interrupt controller, serial interface)
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Nonaka, Yoshiya; Denda, Akihiro; Uesaka, Gakuji; Sakamoto, Yuji; Nii, Noritaka; Satou, Masahiro; Endo, Kazuaki; Katou, Hiroki; Sugino, Ryouji; Sada, Takeshi; Endo, Koji; Nishigata, Junko; Ishiyama, Kunihiro; Morita, Kenji (2002). "HDD-DEH のソフトウェア開発" [Software Development of CD/MP3/Memory Stick Player with HDD] (PDF). Pioneer R&D (in Japanese). Pioneer Corporation. 12 (3): 26–38.
We developed this product which carries new functions, CD( includes MP3CD playback), MagicGate Memory Stick (recording & playback & updating) and HDD (recording & playback), for the first time as a car audio product. This product for the worldwide market is packed into 1DIN size, with standard features (AM/FM Tuner, MOS-FET50Wx4ch amplifier, OrganicEL display, and sound field control DSP) and the new functions. We considered the operation carefully to handle many music files in the HDD easily. We concentrated on making a new field of audio entertainment, and we were the first to introduce this system on the car audio market.
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- V850 Series Development Environment Pamphlet (PDF) (5.00 ed.). Renesas. 2006-02-01.
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- "Trademark Notice". www.renesas.com. Renesas.
"Trademark application T2001-067573". 2001-07-25.
Result: application refused
"V850 Embedded Microcontroller". www.tmdn.org. 2004-12-18.
Result: application refused
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- V850E/PH2: Hardware (PDF) (1.00 ed.). NEC Electronics. January 2007. p. 33.
- Quick time-to-market with Renesas Synergy Platform and Cool Phoenix 3 (PDF) (1.00 ed.). Renesas. October 2016.
- "TMVIEW: PHOENIX 3". www.tmdn.org.
- V850 FAMILY 32-bit Single-Chip Microcontroller Architecture (PDF) (7th ed.). Renesas Electronics. March 2001.
- "RH何某というのはSHのコアなのですか？" [Does RH-something employ SH core?]. Renesas Rulz - Japan. Renesas Electronics. 2017-03-29.
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Engblom, Jakob (2003). "Embedded Systems Computer Architecture" (PDF). Extended Abstract from ESSES 2003.
Code size is an important factor in most embedded designs, and instruction sets are designed and extended with code size in mind. Fairly typically, the NEC V850 architecture uses 16-, 32-, 48-bit, and 64-bit instructions to encode a RISC-style instruction set. The 32-bit ARM and MIPS architecture have been extended with reduced 16-bit instruction sets in order to reduce the code size. Instructions that perform a lot of work, like loading multiple values from the stack, are popular to reduce code size.
- "GCC: V850 Options". gcc.gnu.org. Free Software Foundation, Inc.
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Krämer, Michael (2011-01-21). "Latest 32-bit RISC architecture for automotive expands functionality". EE Times.
All V850 products are upwards compatible. As a result, today's sophisticated components can still execute the same instructions as their forebears. The architecture has undergone continual improvements with extensions to the instruction set, and today it offers computing power of up to 2.6 Dhrystone MIPS/MHz. Further performance increases can be achieved by integrating several of these processor cores on a single chip, delivering twice or even four times more computing power.
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- Matsumoto, Yoichi (1999). "NEXT STEP: NEC'S STRATEGY FOR RISC MICROCOMPUTERS" (PDF). NEC Device Technology International. NEC. 1999 (5).
- V850E1 for Architecture (PDF) (3.01 ed.). Renesas. 2004-02-01.
- "NEC Launches 32-Bit RISC Single-chip Microcontroller for Ultra-low-power Mobile Applications". www.nec.co.jp. NEC: Press Release. 2001-08-23.
- "NEC Releases Java Accelerator for 32-Bit RISC V850 Microcontrollers". www.nec.co.jp. NEC. 2001-11-15.
Aoki, Yayoi (2001-11-30). "US 6,948,034 B2; Method for use of stack" (PDF). pdfpiw.uspto.gov.
The present invention relates to a method for use of a stack in a Java accelerator device.
Mine, Kazumasa (2000-11-21). "US 7,200,741 B1: Microprocessor having main processor and co-processor" (PDF). pdfpiw.uspto.gov. United States Patent and Trademark Office.
With such arrangement, the microprocessor can flexibly deal with various kinds of instruction sets with different architectures such as an instruction set for an interpreter language for realizing a virtual machine for Java and an instruction set for emulating another microprocessor.
- "NEC Electronics Introduces 32-Bit V850E2/ME3 Microcontroller for High-Performance, Real-Time Processing; Most Advanced V850 Microcontroller Enables Performance of 400MIPS at 200MHz. - Free Online Library". www.thefreelibrary.com. 2005.
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Harigai, Hisao; Kusuda, Masahiro; Kojima, Shingo; Moriyama, Masatoshi; Ienaga, Takashi; Yano, Yoichi (1992-10-22). "A low power consumption and low voltage operation 32-bit RISC Microprocessor" (PDF). SIG ARC Technical Reports (in Japanese). Information Processing Society of Japan. 1992 (82 (1992-ARC-096)): 41–48. AN10096105.
An advanced 32-bit RISC microprocessor for embedded control; V810 is introduced in this paper. The V810 has high performance and application specified functions.
V810 dissipates less power than any other RISC chips. The V810 is the first 32-bit RISC microprocessor that operates at 2.2 V.
The V810 chip is fabricated by using 0.8 μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7 mm2 die.
- Kusuda, Masahiro; Hirai, Miho; Suzuki, Hiroaki; Daito, Masayuki; Suzuki, Chika; Kimura, Akiko; Demura, Shigeki; Ishibashi, Takashi; Sato, Syoichiro (September 1992). "低消費電力・低電圧動作のオリジナル32ビットRISCマイクロプロセッサV810" [V810-Low Power Consumption and Low Voltage Operation 32-bit RISC Microprocessor.] (image/jp2). NEC Technical Journal (in Japanese). NEC Corporation. 45 (8): 66–73. ISSN 0285-4139. 000000018731.
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Suzuki, Hiroaki; Suzuki, Chika; Kimura, Akiko; Sato, Syoichiro; Ide, Syuichi; Sakanaka, Yasuhide (1993-01-22). "A 32 - Bit RISC Microprocessor V810 and its design techniques" (PDF). SIG SLDM Technical Reports. 1992-SLDM-065 (in Japanese). Information Processing Society of Japan. 1993 (6): 155–162. AA11451459.
An advanced 32-bit RISC microprocessor for embedded controls ; V810 and its design technique are described in this paper. The V810 is fabricated by using 0.8μm CMOS double metal layer process technology to integrate 240,000 transisters on a 7.7×7.7mm2 die. In design of the V810, we used design automation techniques. The V810 was analyzed for logical correctness and timing constraint before fabrication. Finally, V810 executed realtime-OS and SPEC benchmarks correctly at first silicons.
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Progress of logic/layout synthesis makes it possible to design circuits by Hardware Description Languages (HDLs). When a designed circuit is small, it is synthesized automatically from HDL description. In this paper, to make it clear what kinds of problems are there in designing a large circuit looks like a processor, we design a processor and some components of it by HDLs in RT level and evaluate circuits synthesized by a logic/layout synthesis tool.
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Design Architect by Mentor Graphics Corporation with programs NETED and SYMED. This system is the most universal one of the three [3.3].
Version C1 on HP Unix V10.20 is used (short form MENTOR)
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A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 μm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 × 7.1 mm die.
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"NEC narrows gate length below 0.10 micron | EE Times". EETimes. 2000-10-31.
NEC also will provide internally-developed V850E and VRx CPUs, though Mabuchi said he believes NEC will need to license the ARM9 core to address the market for mobile terminals.
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"NEC Electronics Achieves Key Milestone in ACE-2 Initiative;Reduces System-Level Turnaround Time by More Than 30 Percent
Company Also Unveils Second Phase of Its Open System Design Methodology". www.nec.co.jp. NEC: Press Release. 2000-05-15.
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V850E2M CPU core，max. 266 MHz operation
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This paper describes requirements for real-time UNIX operating systems, design concept and the implementation of RX-UX 832 real-time UNIX operating system for v60/v70 microprocessor which are NEC's 32-bit microprocessors. RX-UX 832 is implemented adopting the building block structure, composed of three modules, real-time kernel, file-server and Unix supervisor. To guarantee a real-time responsibility, several enhancements were introduced such as, fixed priority task scheduling scheme, contiguous block file system and fault tolerant functions.
Thus, RX-UX 832 allows system designers to use standard Unix as its man-machine interface to build fault tolerant systems with sophisticated operability and provides high-quality software applications on the high performance microchips.
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Bunk, Adrian; Torvalds, Linus (2008-07-24). "remove the v850 port". git.kernel.org.
Trying to compile the v850 port brings many compile errors, one of them exists since at least kernel 2.6.19.
There also seems to be no one willing to bring this port back into a usable state.
This patch therefore removes the v850 port.
If anyone ever decides to revive the v850 port the code will still be available from older kernels, and it wouldn't be impossible for the port to reenter the kernel if it would become actively maintained again.
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“We have developed a virtualization technology for our V850 architecture to control multiple systems on a single CPU core with no mutual interference, allowing high speed and composite control for industrial machinery and automotive, where real-time is essential. SYSGO enables us to achieve a scalable CPU architecture with virtualization technology that supports our customers in building flexible development systems.”Michiya Nakamura, General Manager, 1st MCU Business Division, Renesas Electronic Corporation
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•Development process for Wind River Diab Compiler achieves Automotive SPICE Process Capability Level 2 certification.
•New Wind River Diab Compiler ISO 26262 Qualification Kit guides customers in qualifying Diab Compiler for safety-related projects.
•Diab Compiler adds support for Renesas RH850 family microcontrollers.
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In addition to the basic functions as a source level debugger tool, such as program load, program execution, break point control, data display/change, code display/change, there are other functions customized for Midas lab products.
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The vast majority of the competition’s offerings have included a JTAG Test Access Port (TAP). Recently, products have been arriving with more enhanced capabilities, such as N-Wire/N-Trace from NEC, RISCWatch from IBM, and COP from Motorola. These versions of Enhanced JTAG perform relatively the same functions and use the traditional JTAG TAP with a couple additional pins for greater control.
- "64-bit RISC MPU uses superscalar scheme | EE Times". EETimes. 2001-07-30.
- Data sheet: VR5500 64-/32-BIT MICROPROCESSOR (PDF) (2nd ed.). NEC. September 2002. p. 5.
- "Training JTAG Interface" (PDF). lauterbach.com. Lauterbach. pp. 13–15.
- "JTAG IEEE 1149.1 Standard WG". grouper.ieee.org.
- "E1 emulator [R0E000010KCE00]". Renesas Electronics America.
- "PCMCIA N-Wire Card IE-V850E1-CD-NW" (PDF). www.renesas.com. NEC Electronics (Europe) GmbH. 2004.
- "AsmisNetShop ＞ Emulator". sys.ndk-m.com.
- "Product Information | Microcomputer Development Assistance". www.midas.co.jp (in Japanese). Midas lab Inc.
- V850 Debugger and Trace (PDF) (06-Nov-2017 ed.). Lauterbach.
- RH850 Debugger and Trace (PDF) (06-Nov-2017 ed.). Lauterbach.
- "adviceLUNA II". DTS INSIGHT.
- "Support Compilers". DTS INSIGHT.
- "PALMiCE3 V850". www.computex.co.jp.
- "Universal Probe Blue - Supports WATCHPOINT debugger". www.ss-technologies.co.jp (in Japanese). Sohwa & Sophia Technologies.
- "JTAG ICE: PARTNER-Jet". www.kmckk.co.jp (in Japanese). Kyoto Micro Computer.
- PowerTrace for NEXUS (PDF). Lauterbach. 2013-06-14.
- "TESSERA TECHNOLOGY INC". www.tessera.co.jp (in Japanese).
- "ROM Programming Service". MINATO HOLDINGS INC. (in Japanese).
- "What is the IEEE 1532 Standard? | Keysight (formerly Agilent's Electronic Measurement)".
- ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243: Data sheet (PDF) (22.00 ed.). 2015-09-01.
- "List of MCUs supported by Renesas Flash Programmer V2". Renesas Electronics.
- "Renesas Flash Programmer (Programming GUI) [V2]". Renesas Electronics.
- "Renesas Flash Programmer (Programming GUI)". Renesas Electronics.
- PG-FP6 V1.01 Flash Memory Programmer User's Manual (PDF) (1.00 ed.). Renesas. 2018-02-20.
- UPD70P3000 Data Sheet (PDF) (3.00 ed.). Renesas. 1997-08-01.
- UPD70P3002 Data Sheet (PDF) (3.00 ed.). Renesas. 1997-07-01.
- PG-1500 User's Manual (PDF) (4.00 ed.). Renesas. 1997-05-01.
- UPD27C1001A Data Sheet (PDF). NEC.
- Jordan, Larry T., Seeq Technology, Inc. (1981-09-18). "US 4,451,903A: Method and device for encoding product and programming information in semiconductors" (PDF). pdfpiw.uspto.gov. United States Patent and Trademark Office.
- Certain EPROM, EEPROM, Flash Memory and Flash Microcontroller Semiconductor Devices and Products Containing Same, Inv. 337-TA-395. DIANE Publishing. ISBN 9781457824975.
- "VVDI PROG read/write chips with ECU/MCU/MC9S12 Reflash Cables | OBDexpress.co.uk Official Blog". blog.obdexpress.co.uk.
- Renesas V850 Family product page
- Renesas RH850 Family product page
- Renesas "Product Longevity Program (PLP)" official page
- Die photo of V850 (V851 maybe) introduced 1994 by Nikkei BP (in Japanese, registration required)
- Die photo of V853 by NEC's press release (in Japanese)
- Archived pamphlet: V850 (2002-2005) (4th Ed.)
- Archived user' manual: V810 Family Architecture (Rev 1) 1995
- Official user's manual: V850 Architecture (Rev. 7.00) 1994—
- Official user's manual: V850E Architecture (Rev. 6.00) 1996—
- Official user's manual: V850E1 Architecture (Rev. 3.01) 1999—
- Official user's manual: V850ES Architecture (Rev. 4.00) 2002—
- Official user's manual: V850E2 Architecture (Rev. 1.01) 2004—
- Official user's manual: V850E2M Architecture (Rev. 1.00) 2012—
- Official user's manual: V850E2S Architecture (Rev. 1.00) 2014—
- Archived user's manual: V805 & V810 Hardware (Rev. 5) 1996
- Official user's manual: V852 Hardware (Rev. 3) 1995—: PROM variant.
- Official user's manual: V853 Hardware (Rev. 6) 1996—: The first flash memory variant.
- Archived user's manual: NU85E Hardware (Rev. 3) 2000—
- Archived user's manual: Memory Controller Nx85E500
- Archived user's manual: Memory Controller NA85E535, NBA85E535Vxx (Rev. 2) 2001—
- Archived data sheet: V810, Total 66 pages (Rev. 3) 1993
- Present Status of the Embedded CPU in SoC Design, NEC Tech. Journal 1-5 pp.38-45 (Dec. 2006)
- Renesas: V850 Architecture Overview, High performance and Energy Efficient
- Renesas: RH850 Archtecture (RH850 & RL78 -Next Generation of Automotive Microcontrollers), DevCon 2012
- Official user's manual: CA850 Ver. 3.20 - C Compiler Package - Operation (Rev. 1.00) 2007—
- Official user's manual: CC-RH Compiler (Rev. 1.04) 2015—
- Official application note: Using GHS Compiler with RH850 (Rev. 2.00) 2014—
- Official application note: Digital Signal Processing with V850 and V850E Devices (Rev. 1.01) 2005—
- Renesas IE850 (formerly IECUBE2) product page
- Built binaries of GNU Compiler Collection for V850
- Green Hills Software (GHS): V850 and RH850 Embedded Software Solutions
- Midas Lab.: KIT-NA85E2-TP(-H) (in Japanese)
- Midas Lab.: RTE-2000-TP In-Circuit Emulator product page (in Japanese)
- Archived: V850 Series Development Environment (2006-February). Retrieved 2018-01-28.
- SlidePlayer.com: V850E2/Jx4 Series Ultra Low Power 32 bit MCUs – Migration from V850ES/Jx3 MCUs –