|Original author(s)||Ronald G. Minnich, Eric Biederman, Li-Ta (Ollie) Lo, Stefan Reinauer, and the coreboot community|
4.14 / 10 May 2021
|Written in||Mostly C, and about 1% in assembly. Optionally Ada|
|Platform||IA-32, x86-64, ARMv7, ARMv8, MIPS, RISC-V, POWER8|
The software project coreboot, formerly known as LinuxBIOS, is aimed at replacing proprietary firmware (BIOS or UEFI) found in most computers with a lightweight firmware designed to perform only the minimum number of tasks necessary to load and run a modern 32-bit or 64-bit operating system.
Since coreboot initializes the bare hardware, it must be ported to every chipset and motherboard that it supports. As a result, coreboot is available only for a limited number of hardware platforms and motherboard models.
The coreboot project began in the winter of 1999 in the Advanced Computing Laboratory at Los Alamos National Laboratory (LANL), with the goal of creating a BIOS that would start fast and handle errors intelligently. It is licensed under the terms of the GNU General Public License (GPL). Main contributors include LANL, SiS, AMD, Coresystems and Linux Networx, Inc, as well as motherboard vendors MSI, Gigabyte and Tyan, which offer coreboot alongside their standard BIOS or provide specifications of the hardware interfaces for some of their motherboards. Google partly sponsors the coreboot project. CME Group, a cluster of futures exchanges, began supporting the coreboot project in 2009.
Coreboot has been accepted in seven consecutive years (2007–2014) for the Google Summer of Code. Other than the first three models, all Chromebooks run coreboot. Code from Das U-Boot has been assimilated to enable support for processors based on the ARM instruction set.
CPU architectures supported by coreboot include IA-32, x86-64, ARM, ARM64, MIPS and RISC-V. Supported system-on-a-chip (SOC) platforms include AMD Geode, starting with the Geode GX processor developed for the OLPC. Artec Group added Geode LX support for its ThinCan model DBE61; that code was adopted by AMD and further improved for the OLPC after it was upgraded to the Geode LX platform, and is further developed by the coreboot community to support other Geode variants. Coreboot can be flashed onto a Geode platform using Flashrom.
From that initial development on AMD Geode based platforms, coreboot support has been extended onto many AMD processors and chipsets. The processor list includes Family 0Fh and 10h (K8 core), and recently Family 14h (Bobcat core, Fusion APU). Coreboot support also extends to AMD chipsets: RS690, RS7xx, SB600, and SB8xx.
AMD Generic Encapsulated Software Architecture (AGESA)—a bootstrap protocol by which system devices on AMD64 mainboards are initialized—was open sourced in early 2011, aiming to provide required functionality for coreboot system initialization on AMD64 hardware. However, such releases never became the basis for future development by AMD, and were subsequently halted.
Devices that can be preloaded with coreboot or one of its derivatives include some x86-based Chromebooks, the Libreboot X200 and T400 (rebranded ThinkPad X200 and T400, respectively, available from Minifree, previously known as Gluglug), OLPC XO from the One Laptop per Child initiative, ThinCan models DBE61, DBE62 and DBE63, and fanless server/router hardware manufactured by PC Engines. All Librem laptops come with coreboot. 
Coreboot typically loads a Linux kernel, but it can load any other stand-alone ELF executable, such as iPXE, gPXE or Etherboot that can boot a Linux kernel over a network, or SeaBIOS that can load a Linux kernel, Microsoft Windows 2000 and later, and BSDs (previously, Windows 2000/XP and OpenBSD support was provided by ADLO). Coreboot can also load a kernel from any supported device, such as Myrinet, Quadrics, or SCI cluster interconnects. Booting other kernels directly is also possible, such as a Plan 9 kernel. Instead of loading a kernel directly, coreboot can pass control to a dedicated boot loader, such as a coreboot-capable version of GNU GRUB 2.
Coreboot is written primarily in C, with a small amount of assembly code. Choosing C as the primary programming language enables easier code audits when compared to contemporary PC BIOS that was generally written in assembly, which results in improved security. There is build and runtime support to write parts of coreboot in Ada to further raise the security bar, but it is currently only sporadically used. The source code is released under the GNU GPL version 2 license.
Coreboot performs the absolute minimal amount of hardware initialization and then passes control to the operating system. As a result, there is no coreboot code running once the operating system has taken control. A feature of coreboot is that the x86 version runs in 32-bit mode after executing only ten instructions (almost all other x86 BIOSes run exclusively in 16-bit mode). This is similar to the modern UEFI firmware, which is used on newer PC hardware.
By itself, coreboot does not provide BIOS call services. The SeaBIOS payload can be used to provide BIOS calls and thus allow coreboot to load operating systems that require those services, such as Windows 2000/XP/Vista/7 and BSDs. However, most modern operating systems access hardware in another manner and use BIOS calls only during early initialization and as a fallback mechanism.
- Bootblock stage: Prepare to obtain Flash access and look up the ROM stage to use
- ROM stage: Memory and early chipset init (a bit like PEI in UEFI)
- RAM stage: CPU, chipset, mainboard and peripheral init, PCI resource assignment, ACPI table creation, SMM handler (a bit like DXE stage in UEFI)
The most difficult hardware that coreboot initializes is the DRAM controllers and DRAM. In some cases, technical documentation on this subject is NDA restricted or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's general purpose registers or Cache-as-RAM as temporary storage.
With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache-as-RAM mode initialization is specific to CPU architectures, thus more generic than DRAM initialization, which is specific to each chipset and mainboard.
For most modern x86 platforms, closed source binary-only components provided by the vendor are used for DRAM setup. For Intel systems, FSP-M is required, while AMD has no current support. Binary AGESA is currently used for proprietary UEFI firmware on AMD systems, and this model is expected to carry over to any future AMD-related coreboot support.
Developing and debugging coreboot
Since coreboot must initialize the bare hardware, it must be ported to every chipset and motherboard that it supports. Before initializing RAM, coreboot initializes the serial port (addressing cache and registers only), so it can send out debug text to a connected terminal. It can also send byte codes to port 0x80 that are displayed on a two-hex-digit display of a connected POST card.
Another porting aid was the commercial "RD1 BIOS Savior" product from www.ioss.com.tw, (not to be confused with US Interagency OPSEC Support Staff at www.iad.gov/ioss/) which was a combination of two boot memory devices that plugs into the boot memory socket and has a manual switch to select between the two devices. The computer could boot from one device, and then the switch can be toggled to allow the computer to reprogram or "flash" the second device. A more expensive alternative is an external EEPROM/NOR flash programmer.
There are also CPU emulators that either replace the CPU or connect via a JTAG port, with the Sage SmartProbe being an example. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device.
Coreboot can load a payload, which may be written using the libpayload helper library. Existing payloads include the following:
- SeaBIOS, a tiny implementation of x86 BIOS, written mostly in 16-bit C using the GNU C compiler
- TianoCore, a free and open-source implementation of UEFI
- OpenBIOS, a free and open-source implementation of Open Firmware
- GNU GRUB, a bootloader
- FILO, a GRUB-like bootloader with USB boot support
- Etherboot, it can boot an operating system over the network
- gPXE/iPXE, the successor to Etherboot, works when run under SeaBIOS or TianoCore
- Depthcharge is used by Google for Chrome OS
- A branch of Das U-Boot was used by Google for Chromium OS in the past
European Coreboot Conference
One physical meeting is the European Coreboot Conference which was organized in October 2017 and lasted for 3 days.
|Event and year||Date||Host city||Venue||Resources||Themes|
|ECC2017||26.10. – 29.10||Bochum, Germany||RUB Convention Center||https://ecc2017.com|
Coreboot has a number of variants from its original code base each with slightly different objectives:
- librecore - A variant with more focus on freedom, non-x86 instruction set computers, and firmware development frameworks.
- Libreboot - A variant with a primary focus to remove all binary blobs.
Libreboot has been established as a distribution of coreboot without proprietary binary blobs. Libreboot is not a straight fork of coreboot; instead, it is a parallel effort that works closely with and re-bases every so often on the latest coreboot as the upstream supplier, with patches merged upstream whenever possible. In addition to removing proprietary software, libreboot also attempts to make coreboot easy to use by automating the build and installation processes.
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The success out of Coreboot recently is Google providing Sandy/Ivy Bridge support for Coreboot. Google's planning to begin shipping new Intel "Chromebooks" that will use Coreboot. Google likes Coreboot for the faster start-up time, among other benefits.
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- SeaBIOS (previously known as LegacyBIOS) is an open-source legacy BIOS implementation
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- commit adding that support
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