OpenRISC
OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support [1].
A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. The hardware design was released under the GNU Lesser General Public License, while the models and firmware were released under the GNU General Public License. A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups demonstrated ORPSoC and other OR1200 based designs running on FPGA [2][3].
Commercial implementations
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC (who also maintain the opencores.org website) and the BA12, BA14 and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12. Flextronics International and Jennic Limited manufactured the OpenRISC as part of an ASIC.
![[icon]](/wiki/File:Wiki_letter_w_cropped.svg){kind=small} | This section needs expansion with: more commercial examples. You can help by adding to it. (March 2009) |
Tool chain support
The OpenCores community have ported the GNU toolchain to OpenRISC to support development in C. Using this tool chain, uClibc, Linux and µClinux have also been ported to the processor. Dynalith provides OpenIDEA, a graphical development environment based on this tool chain.
The OpenCores community also provide an instruction set simulator and cycle accurate model of both the OpenRISC 1200 and ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative set up by Imperas.
References
- ^ Damjan Lampret et al., "OpenRISC 1000 Architecture Manual", Rev 1.3, 15 Nov 2007. Available from the OpenCores website (requires free registration) [1]
- ^ Patrick Pelgrims, Tom Tierens and Dries Driessens, "Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGA’s", De Nayer Instituut, Hogeschool voor Wetenschap & Kunst, 2004. Available online [2]
- ^ Xiang Li and Lin Zuo, "Open source embedded platform based on OpenRISC and DE2-70", Masters dissertation, SoC program, KTH, Sweden. Available online [3]
See also
External links
- OpenRISC 1200 at the Open Cores Website
- GNU toolchain building guides
- Beyond Semiconductor commercial fabless semiconductor company founded by the developers of OpenRISC
- Dynalith Systems company website.
- Imperas company website.
- Flextronics International company website
- Jennic company website
- ORSoC company website. ORSoC also maintain the opencores.org website.
- Eetimes article