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Intel SpeedStep
Design firm Intel
Introduced Q1 2005[1]
Type Dynamic frequency scaling

SpeedStep is a series of dynamic frequency scaling technologies (codenamed Geyserville[2] and including SpeedStep, SpeedStep II, and SpeedStep III) built into some Intel microprocessors that allow the clock speed of the processor to be dynamically changed (to different P-states) by software. This allows the processor to meet the instantaneous performance needs of the operation being performed, while minimizing power draw and heat generation.

Enhanced Intel SpeedStep is sometimes abbreviated as EIST. Intel's trademark of "SpeedStep" expired in 2012.


Running a processor at high clock speeds allows for better performance. However, when the same processor is run at a lower frequency (speed), it generates less heat and consumes less power. In many cases, the core voltage can also be reduced, further reducing power consumption and heat generation. By using SpeedStep, users can select the balance of power conservation and performance that best suits them, or even change the clock speed dynamically as the processor burden changes.

The power consumed by a CPU with a capacitance C, running at frequency f and voltage V is approximately:[3]

For a given processor, C is a fixed value. However, V and f can vary considerably. For example, for a 1.6 GHz Pentium M, the clock frequency can be stepped down in 200 MHz decrements over the range from 1.6 to 0.6 GHz. At the same time, the voltage requirement decreases from 1.484 to 0.956 V. The result is that the power consumption theoretically goes down by a factor of 6.4. In practice, the effect may be smaller because some CPU instructions use less energy per tick of the CPU clock than others. For example, when an operating system is not busy, it tends to issue x86 halt (HLT) instructions, which suspend operation of parts of the CPU for a time period, so it uses less energy per tick of the CPU clock than when executing productive instructions in its normal state. For a given rate of work, a CPU running at a higher clock rate will execute a greater proportion of HLT instructions. The simple equation which relates power, voltage and frequency above also does not take into account the static power consumption of the CPU. This tends not to change with frequency, but does change with temperature and voltage. Hot electrons, and electrons exposed to a stronger electric field are more likely to migrate across a gate as "gate leakage" current, leading to an increase in static power consumption.

Older processors such as the Pentium 4-M, which use older versions of SpeedStep, have fewer clock-speed increments. SpeedStep technology is partly responsible for the reduced power consumption of Intel’s Pentium M processor, part of the Centrino brand.


Pentium 4 (Prescott)[edit]

EIST was introduced in several Prescott 6 series in the first quarter of 2005, namely the Pentium 4 660.[1]


Most Pentium, Core Duo and Solo processors support EIST.[citation needed]

Merom, Conroe and Allendale, Penryn and Wolfdale[edit]

Most Core 2 Duo, Quad, Extreme and Solo processors support EIST. Celeron started supporting EIST in Allendale.[citation needed]

Nehalem, Sandy Bridge, Ivy Bridge, Haswell and Skylake[edit]

All Core i3, i5, i7, Xeon, Celeron and Pentium processors support EIST.[citation needed]

Known issues[edit]

Microsoft has reported that there may be problems previewing video files when SpeedStep (or the AMD equivalent PowerNow!) is enabled under Windows 2000 or Windows XP.[4]

Hosting multiplayer game servers, players experience "lag" and bad "hit register" while connected one of these servers which run Intel SpeedSteps with low frequency (GHz)

Operating system support[edit]

  • The BSD kernels have full SpeedStep support integration.[when?]
  • Linux has fully supported SpeedStep since kernel 2.6.[citation needed]
  • Mac OS X also has SpeedStep built into the kernel, since the release of the Intel version of Mac OS X 10.4 and is already enabled. It cannot be controlled if the system preference is "Energy Saver".[citation needed]
  • Solaris has supported SpeedStep since OpenSolaris SXDE 9/07.[5]
  • Older versions of Microsoft Windows, Windows 2000 and earlier, need a special driver and dashboard application to access the SpeedStep feature. Intel's website specifically states that such drivers must come from the computer manufacturer; there are no generic drivers supplied by Intel which will enable SpeedStep for older Windows versions if one cannot obtain a manufacturer's driver.[6][7]
  • Under Microsoft Windows XP, SpeedStep support is built into the power management console under the control panel. In Windows XP a user can regulate processor speed indirectly by changing power schemes. The "Home/Office Desk" setting disables SpeedStep, the "Portable/Laptop" power scheme enables SpeedStep, and the "Max Battery" uses SpeedStep to slow the processor to minimal power levels as the battery weakens.[8] The SpeedStep settings for power schemes, either built-in or custom, cannot be modified from the control panel's GUI, but can be modified using the POWERCFG.EXE command-line utility.[9]

In contrast, AMD continues to supply and support drivers for its competing PowerNow! technology that will work on Windows 2000, ME, 98, and NT.[10][11]


  • V1.1 is used by second generation Pentium III processors. It enables the CPU to switch between two modes: high and low frequency. This is done by modifying the CPU's multiplier.
  • V2.1 (Enhanced SpeedStep) is used in Pentium III-Mobile processors and is similar to the previous version, but in the low frequency mode the CPU also uses a different voltage than the high frequency mode.
  • V2.2 is adapted for Pentium 4-Mobile processors.
  • V3.1 (EIST) is used with the first and second generation of Pentium M processors (Banias and Dothan cores, used in Centrino platforms). With this technology, the CPU varies its frequency (and voltage) between about 40% and 100% of its base frequency in increments of 100 MHz (for Banias core) or 133 MHz (for Dothan core). With this technology, Intel also introduces realtime Level 2 cache capacity variation, further improving power savings.
  • V3.2 (Enhanced EIST) is adapted for multi-core processors with unified Level 2 cache.

See also[edit]


External links[edit]