Advanced Microcontroller Bus Architecture

The Advanced Microcontroller Bus Architecture (AMBA) is used as the on-chip bus in system-on-a-chip (SoC) designs. Since its inception, the scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range of ASIC and SoC parts including applications processors used in modern portable mobile devices like smartphones.

The AMBA protocol is an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.

AMBA was introduced by ARM Ltd in 1996. The first AMBA buses were Advanced System Bus (ASB) and Advanced Peripheral Bus (APB). In its 2nd version, AMBA 2, ARM added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. In 2003, ARM introduced the 3rd generation, AMBA 3, including AXI to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution. These protocols are today the de-facto standard for 32-bit embedded processors because they are well documented and can be used without royalties.

Design principles

The important aspect of a SoC is not only which components or blocks it houses, but also how they are interconnected. AMBA is a solution for the blocks to interface with each other.

The objective of the AMBA specification is to:

• facilitate right-first-time development of embedded microcontroller products with one or more CPUs, GPUs or signal processors,
• be technology independent, to allow reuse of IP cores, peripheral and system macrocells across diverse IC processes,
• encourage modular system design to improve processor independence, and the development of reusable peripheral and system IP libraries
• minimize silicon infrastructure while supporting high performance and low power on-chip communication.

AMBA protocol specifications

The AMBA specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. It is supported by the ARM Limited corporation with wide cross-industry participation.

The AMBA 4.0 specification defines five buses/interfaces:

• Advanced eXtensible Interface (AXI)
• Advanced High-performance Bus (AHB)
• Advanced System Bus (ASB)
• Advanced Peripheral Bus (APB)
• Advanced Trace Bus (ATB).

The timing aspects and the voltage levels on the bus are not dictated by the specifications.

Advanced eXtensible Interface (AXI)

AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features which make it very suitable for high speed sub-micrometer interconnect:

• separate address/control and data phases
• support for unaligned data transfers using byte strobes
• burst based transactions with only start address issued
• issuing of multiple outstanding addresses
• easy addition of register stages to provide timing closure.

Advanced High-performance Bus (AHB)

AHB is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2 published by ARM Ltd company.

In addition to previous release, it has the following features:

• single edge clock protocol
• split transactions
• several bus masters
• burst transfers
• pipelined operations
• single-cycle bus master handover
• non-tristate implementation
• large bus-widths (64/128 bit).

A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only two bus-cycles). Access to the target device is controlled through a MUX (non-tristate), thereby admitting bus-access to one bus-master at a time.

AHB-Lite is a subset of AHB which is formally defined in the AMBA 3 standard. This subset simplifies the design for a bus with a single master. The ARM AMBA Support FAQ page includes notes on how to integrate a full AHB master into an AHB-lite system and vice versa.

Advanced Peripheral Bus (APB)

APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced low complexity signal list, for example no bursts. it has to support 32bit and 66mhz signal

AMBA products

A family of synthesizable intellectual property (IP) cores AMBA Products licensable from ARM Limited that implement a digital highway in an SoC for the efficient moving and storing of data using the AMBA protocol specifications. The AMBA family includes AMBA Network Interconnect (NIC-301), SDRAM and FLASH memory controllers (DMC-34x, SMC-35x), DMA controllers (DMA-230, DMA-330), level 2 cache controllers (L2C-310), etc.

Some manufacturers utilize AMBA buses for non-ARM designs. As an example Infineon uses an AMBA bus for the ADM5120 SoC based on the MIPS architecture.

Competitors

• Opencores Wishbone bus - Free and open bus architecture (formerly from Silicore)
• IBM CoreConnect bus technology, used in Power systems, but also in many other SoCs like systems with the Xilinx MicroBlaze or similar cores
• IDT IPBus
• Altera Avalon - proprietary bus system for Alteras Nios II-SoCs
• OCP [1] Open Core Protocol

See also

• Functional specification

External links

• AMBA Specification - of ARM
• AMBA of ARM
• AMBA Documentation - from ARM
• AMBA 2 Specification - from ARM
• AMBA 3 and 4 Specification - from ARM
• AHB To Wishbone project page - AHB to Wishbone bridge
• APB eVC (e Verification Component)