CDC 6000 series
The CDC 6000 series was a family of mainframe computers manufactured by Control Data Corporation in the 1960s. It consisted of CDC 6400, CDC 6500, CDC 6600 and CDC 6700 computers, which all were extremely rapid and efficient for their time. Each was a large, solid-state, general-purpose, digital computer that performed scientific and business data processing as well as multiprogramming, multiprocessing, time-sharing, and data management tasks under the control of the operating system called SCOPE (Supervisory Control Of Program Execution).
The CDC 6000 series computer is composed of four main functional devices: the central memory, one or two high speed central processors, seven to ten peripheral processors (Peripheral Processing Unit, or PPU), and a display console. The four computer types differ primarily in the number of and kind of central processor. It had a distributed architecture and was a reduced instruction set (RISC) machine many years before such a term was invented.
The first member of the CDC 6000 series was the first supercomputer CDC 6600, designed by Seymour Cray and James E. Thornton in Chippewa Falls, Wisconsin. It was introduced in September 1964 and performed up to three million instructions per second, three times faster than the IBM Stretch, the speed champ for the previous couple of years. It remained the fastest machine for five years until the CDC 7600 was launched. The machine was Freon refrigerant cooled. Control Data manufactured about 100 machines of this type, selling for $6 to $10 million each.
The next system to be introduced was the CDC 6400, delivered in April 1966. The 6400 central processor was a slower, less expensive, implementation with serial processing, rather than the 6600s parallel functional units. All other aspects of the 6400 were identical to the 6600. Then followed a machine with dual 6400-style central processors, the CDC 6500, designed principally by James E. Thornton, in October 1967. And finally, the CDC 6700, with both a 6600-style CPU and a 6400-style CPU, was released in October 1969.
Subsequent modifications to the series in 1969 included the extension to 20 peripheral and control processors with 24 channels. (A 30-PPU 6600 machine was operated by Control Data's Software Research Lab during 1971-1973, but this version was never sold commercially.) Control Data also marketed a CDC 6400 with a smaller number of peripheral processors, the CDC 6415-7 with seven peripheral processors to reduce cost.
|P||A0||B0 = 0|
The central processor was the high-speed arithmetic unit that functioned as the workhorse of the computer. It performed the addition, subtraction, and logical operations and all of the multiplication, division, incrementing, indexing, and branching instructions for user programs. Note that in the CDC 6000 architecture, the central processing unit performed no I/O operations. I/O was totally asynchronous, and performed by peripheral processors.
A 6000 series CPU contained 24 operating registers, designated X0-X7, A0-A7, and B0-B7. The eight X registers were each 60 bits long, and used for most data manipulation—both integer and floating point. The eight B registers were 18 bits long, and generally used for indexing and address storage. Register B0 was hard-wired to always return 0. By software convention, register B1 was generally set to 1. (This often allowed the use of 15-bit instructions instead of 30-bit instructions.) The eight 18-bit A registers were 'coupled' to their corresponding X registers in an interesting way: setting an address into any of registers A1 through A5 caused a memory load of the contents of that address into the corresponding X registers. Likewise, setting an address into registers A6 and A7 caused a memory store into that location in memory from X6 or X7. Registers A0 and X0 were not coupled in this way, so could be used as scratch registers. However A0 and X0 were used when addressing CDCs Extended Core Storage (ECS).
Instructions were either 15 or 30 bits long, so there could be up to 4 instructions per 60-bit word. The op codes were 6 bits long. The remainder of the instruction was either three 3-bit register fields (two operands and one result), or two registers with an 18-bit immediate constant. All instructions were 'register to register'. For example the following COMPASS code loads two values from memory, performs a 60-bit integer add, then stores the result:
SA1 X "SET" REGISTER A1 TO THE ADDRESS OF X (30 bits) SA2 Y "SET" REGISTER A2 TO THE ADDRESS OF Y (30 bits) IX6 X1+X2 LONG INTEGER ADD X AND Y, RESULT INTO X6 (15 bits) SA6 Z "SET" REGISTER A6 TO THE ADDRESS OF Z (30 bits)
The central processor used in the CDC 6400 series contained a unified arithmetic element which performed one machine instruction at a time. Depending on instruction type, an instruction could take anywhere from a relatively fast 5 clock cycles (18-bit integer arithmetic) to as many as 68 clock cycles (60-bit population count). The CDC 6500 was identical to the 6400, but included two identical 6400 CPUs. Thus the CDC 6500 could nearly double the computational throughput of the machine.
The CDC 6600 computer, like the CDC 6400, has just one central processor. However, its central processor offered much greater efficiency. The processor was divided into 10 individual functional units, each of which was designed for a specific type of operation. The function units provided were: branch, Boolean, shift, long integer add, floating-point add, floating-point divide, two floating-point multipliers, and two increment (18-bit integer add) units. Functional unit latencies were between a very fast 3 clock cycles (increment add) and 29 clock cycles (floating-point divide).
The 6600 processor could issue a new instruction every clock cycle, assuming that various processor (functional unit, register) resources were available. These resources were kept track of by a scoreboard mechanism. Also contributing to keeping the issue rate high was an instruction stack, which cached the contents of several instruction words. Small loops could reside entirely within the stack, eliminating memory latency from instruction fetches.
Both the 6400 and 6600 CPUs had a cycle time of 100 ns (10 MHz). Due to the serial nature of the 6400 CPU, its exact speed was heavily dependent on instruction mix, but generally around 1 MIPS. Floating-point additions were fairly fast at 11 clocks, however floating-point multiplication was very slow at 57 clocks. Thus its floating point speed would depend heavily on the mix of operations and could be under 200 kFLOPS. The 6600 was, of course, much faster. With good compiler instruction scheduling, the machine could approach its theoretical peak of 10 MIPS. Floating-point additions took 4 clocks, and floating-point multiplies took 10 clocks (but there were two multiply functional units, so two operations could be processing at the same time.) The 6600 could therefore have a peak floating point speed of 2-3 MFLOPS.
The CDC 6700 computer combined the best features of the other three computers. Like the CDC 6500, it had two central processors. One was a CDC 6400/CDC 6500 central processor with the unified arithmetic section; the other was the more efficient CDC 6600 central processor. The combination made the CDC 6700 the fastest and the most powerful of the four CDC 6000 series.
|CDC 6400||12||10||1||24||Unified Arithmetic Section|
|CDC 6500||12||10||1||24||Unified Arithmetic Section|
|24||Unified Arithmetic Section|
|CDC 6600||12||10||1||24||Add, Multiply (2x), Divide, Long add, Shift, Boolean, Increment (2x), Branch|
|CDC 6700||12||10||1||24||Unified Arithmetic Section|
|24||Add, Multiply (2x), Divide, Long add, Shift, Boolean, Increment (2x), Branch|
In all the CDC 6000 series computers, the central processor communicates with around seven simultaneously active programs (jobs), which reside in central memory. Instructions from these programs are read into the central processor registers and are executed by the central processor at scheduled intervals. The results are then returned to central memory.
Information is stored in central memory in the form of words. The length of each word is 60 binary digits (bits). The highly efficient address and data control mechanisms involved permit a word to be moved into or out of central memory up to one every 100 nanoseconds.
An extended core storage unit (ECS) provides additional memory storage and enhances the powerful computing capabilities of the CDC 6000 series computers.
The central processor shares access to central memory with ten peripheral processors. Each peripheral processor is an individual computer with its own 1 μs memory of 4K words, each with 12 bits. (They were somewhat similar to CDC 160A minicomputers, sharing the 12 bit word length and portions of the instruction set.) Peripheral processors are used primarily for input/output: the transfer of information between central memory and peripheral devices such as disks and magnetic tape units. They relieve the central processor of all input/output tasks, so that it can perform calculations while the peripheral processors are engaged in input/output functions. This feature promotes rapid overall processing of user programs. Each peripheral processor can add, subtract, and perform logical operations. Special instructions performed data transfer between processor memory and peripheral devices at up to 1 μs per word. The peripheral processors were collectively implemented as a Barrel processor. Each executes routines independently of the others. (For comparison, on the IBM 360 series of machines, these processors were called channels.) They are a loose predecessor of bus mastering or Direct memory access.
Nearly all of the operating system ran on the PP's; thus leaving the full power of the Central Processor available for user programs.
For input or output, each peripheral processor accesses a peripheral device over a communication link called a data channel. One peripheral device can be connected to each data channel; however, a channel can be modified with hardware to service more than one device.
Each peripheral processor can communicate with any peripheral device if another peripheral processor is not using the data channel connected to that device. In other words, only one peripheral processor at a time can use a particular data channel.
In addition to communication between peripheral devices and peripheral processors, communication takes place between the computer operator and the operating system. This was made possible by the computer console, which had two CRT screens.
This display console was a significant departure from conventional computer consoles of the time, which contained hundreds of blinking lights and switches for every state bit in the machine. (See Front panel for an example.) By comparison, the 6000 series console was an elegant design; simple, fast and reliable.
The console screens were calligraphic, not raster based. Analog circuitry actually steered the electron beams to draw the individual characters on the screen. One of the peripheral processors ran a dedicated program called "DSD" (Dynamic System Display), which drove the console. Coding in DSD needed to be fast as it needed to continually redraw the screen quickly enough to avoid visible flicker.
DSD displayed information about the system and the jobs in process. The console also included a keyboard through which the operator could enter requests to modify stored programs and display information about jobs in or awaiting execution.
A full screen editor, called O26 (after the IBM model 026 key punch, with the first character made alphabetic due to operating system restrictions), could be run on the operator console. This text editor appeared in 1967—which made is one of the first full screen editors. (Unfortunately, it took CDC another 15 years to offer FSE, a full screen editor for normal time-sharing users on CDCs Network Operating System.)
There were also a variety of games that were written using the operator console. These included BAT (a baseball game), KAL (a kaleidoscope), DOG (Snoopy flying his doghouse across the screens), ADC (Andy Capp strutting across the screens), EYE (changed the screens into giant eyeballs, then winked them), PAC (a Pac-man-like game), and more.
The minimum hardware requirements of a CDC 6000 series computer system consists of the computer, including 32,768 words of central memory storage, any combination of disks, disk packs or drums to provide 24 million characters of mass storage, a punched card reader, punched card punch, printer with controllers, and two 7-track magnetic tape units. Larger systems can be obtained by including optional equipment such as: additional central memory, extended core storage (ECS), additional card readers, punches, printers, and tape units. Graphic plotters and microfilm recorders are also available.
- CONTROL DATA 6400/6500/6600 Computer Systems Reference Manual, Publication No. 60100000 D, 1967
- CONTROL DATA 6400/6500/6600/6700 Computer Systems, SCOPE 3.3 User’s Guide, Publication No. 60252700 A, 1970
- CONTROL DATA 6400/6500/6600/6700 Computer Systems, SCOPE Reference Manual, Publication No. 60305200, 1971
- Computer history on CDC 6600
- Gordon Bell on CDC computers
- Neil R. Lincoln with 18 Control Data Corporation (CDC) engineers on computer architecture and design, Charles Babbage Institute, University of Minnesota. Engineers include Robert Moe, Wayne Specker, Dennis Grinna, Tom Rowan, Maurice Hutson, Curt Alexander, Don Pagelkopf, Maris Bergmanis, Dolan Toth, Chuck Hawley, Larry Krueger, Mike Pavlov, Dave Resnick, Howard Krohn, Bill Bhend, Kent Steiner, Raymon Kort, and Neil R. Lincoln. Discussion topics include CDC 1604, CDC 6600, CDC 7600, and Seymour Cray.