Intel Tick-Tock

From Wikipedia, the free encyclopedia
Jump to: navigation, search

"Tick-Tock" is a model adopted by chip manufacturer Intel Corporation since 2007 to follow every microarchitectural change with a die shrink of the process technology. Every "tick" is a shrinking of process technology of the previous microarchitecture and every "tock" is a new microarchitecture.[1] Every year, there is expected to be one tick or tock.[1]

Contents

Roadmap[edit]

Architectural change Fabrication process Microarchitecture Codename Release date Processors
8P/4P Server 4P/2P Server/WS Enthusiast/WS Desktop Mobile Marketing names
Tick Die shrink 65 nm P6, NetBurst Presler, Cedar Mill, Yonah January 5, 2006 Presler Cedar Mill Yonah
Tock New microarchitecture Core Conroe July 27, 2006[2] Tigerton Woodcrest
Clovertown
Kentsfield Conroe Merom
Tick Die shrink 45 nm Penryn November 11, 2007[3] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock New microarchitecture Nehalem Nehalem November 17, 2008[4] Beckton Gainestown Bloomfield Lynnfield Clarksfield
Tick Die shrink 32 nm Westmere January 4, 2010[5][6] Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Tock New microarchitecture Sandy Bridge Sandy Bridge January 9, 2011[7] (Skipped)[8] Sandy Bridge-EP Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick Die shrink 22 nm Ivy Bridge April 29, 2012 Ivy Bridge-EX[9] Ivy Bridge-EP[9] Ivy Bridge-E[10] Ivy Bridge
Tock New microarchitecture Haswell Haswell June 2, 2013 Haswell-DT[11]
  • Haswell-MB (notebooks)
  • Haswell-LP (ultrabooks)[11]
Tick Die shrink 14 nm[12] Broadwell[13] 2014[5]
Tock New microarchitecture Skylake[13] Skylake[13] 2015
Tick Die shrink 10 nm[14] Skymont[13] 2016
Tock New microarchitecture 2017
Tick Die shrink 7 nm[14] 2018
Tock New microarchitecture 2019
Tick Die shrink 5 nm[14] 2020
Tock New microarchitecture 2021
Intel processor roadmap
Intel CPU core roadmaps from NetBurst and P6 to Skymont


See also[edit]

References[edit]

External links[edit]