Intel Tick-Tock

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"Tick-Tock" is a model, developed by Ashwani Gupta[citation needed] of Jones Farm 5 (Hillsboro, Oregon) and adopted by chip manufacturer Intel Corporation since 2007 to follow every microarchitectural change with a die shrink of the process technology. Every "tick" is a shrinking of process technology of the previous microarchitecture and every "tock" is a new microarchitecture.[1] Every year, there is expected to be one tick or tock.[1]

Contents

[edit] Roadmap

Architectural change Codename Fabrication process Release date Processors
8P/4P Server 4P/2P Server/WS Enthusiast/WS Desktop Mobile Marketing names
Tick Die shrink Presler, Cedar Mill, Yonah 65 nm January 5, 2006 Presler Cedar Mill Yonah
Tock New microarchitecture Core July 27, 2006[2] Kentsfield Conroe Merom
Tick Die shrink Penryn 45 nm November 11, 2007[3] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock New microarchitecture Nehalem November 17, 2008[4] Beckton Gainestown Bloomfield Lynnfield Clarksfield
Tick Die shrink Westmere 32 nm January 4, 2010[5][6] Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Tock New microarchitecture Sandy Bridge January 9, 2011[7] Sandy Bridge-EP Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick Die shrink Ivy Bridge 22 nm Q2 2012
Tock New microarchitecture Haswell Q1 2013
Tick Die shrink Broadwell[8] 14 nm[9] 2014[5]
Tock New microarchitecture Skylake[8] 2015
Tick Die shrink Skymont[8] 10 nm[9] 2016
Tock New microarchitecture 2017

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[edit] External links

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