Talk:Intel Core (microarchitecture)

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4GHZ Processors[edit]

The introduction talks about Devil's Canyon being the first to reach netburst clocks. That's not actually the case. The Xeon 5698 (Westmere) was a 4.4GHZ dual core part

Nehalem has 16 stages?[edit]

Contradicted by source which, upon closer inspection, states that Nehalem's pipeline has 20-24 stages. Unfortunately, Intel Architectures Software Developer's Manual does not clearly indicate the number of pipeline stages.

Data pipeline is 14 stages?[edit]

I seriously doubt this. Perhaps the _instruction pipeline_ is 14 stages but I doubt the _data pipeline is. I didn't change the artical because I didn't research this. Also the width should be noted.

"Intel P8" should redirect to Conroe[edit]

This article should be put into Conroe to conform to the standard of articles on microprocessor architectures in Wikipedia. Intel processor microarchitectures are referred to by their code names in Wikipedia, not by their generation number. For example, Intel P7 directs the viewer to Netburst, and Intel P5 does not exist, the P5 architecture is described under Pentium. Intel P6 is also very similar in that only links to the names of processors of that generation are listed with architectual improvements described at each processor instead of the features of the artcitecture described directly at Intel P6.

This article seems slightly more detailed than Conroe, so the improvements made to this article should be integrated into Conroe. This is the reason I suggested the article for merging instead of deletion.

I respectfully disagree. Conroe is not the name of the eight generation architecture, only the code name of the first desktop chip to use the new architecture. Unfortunately, Conroe does not represent all the chips of the new architecture, and a broader article to represent them all is needed. There will be other chips to succeed Merom, Conroe, and Woodcrest that will use the new architecture. Conroe actually reminds me of Willamette, the first ever NetBurst chip in 2000, and that chip did not even merit its own article. On the other hand, Intel P8 represents the whole architecture, at least until a finalized brand name is released. But until then, the architecture is Intel P8. The two can not be merged. Would you like to just keep the two articles distinct? --Noypi380 05:55, 25 August 2005 (UTC)[reply]

Conroe redirected to P8 instead[edit]

It was discussed instead in Talk:Conroe that Conroe should redirect to Intel P8. Any objections? --Noypi380 14:32, 27 August 2005 (UTC)[reply]

Disagree. Conroe is the name of the first processor which will use the new architecture, there is no evidence that that will be the name of the architecture itself (Willamette was the first P4 but the architecture is Netburst, not Willamette). P8 should remain a separate article until Intel reveals the codename for the new architecture (ala Netburst) at which point P8 should be merged with that codename. --Defsac 12:18, 26 September 2005 (UTC)[reply]

I agree with Noypi380. Conroe is an implementation of P8 architecture. At this stage, and since the P8 article is still relatively short, it would be useful to merge the content of Conroe into a new section in Intel P8 and redirect from Conroe. This will allow users to find all information in one place. --Smiley77 20:56, 1 December 2005 (UTC)[reply]

I Disagree. Intel procesor generations should be grouped by Family CPUID. And this is in Conroe '6' - same as in P II and P III etc. P6 = FamilyID 6, P7 (Netburst based) = FamilyID F. —The preceding unsigned comment was added by 83.31.209.119 (talk • contribs) 12:21, 14 July 2006 (UTC).[reply]

Disagree. "Conroe" is also the name of a town in Texas, and the Conroe page is currently a disambiguation page that points both to the Conroe, Texas page and the page for Intel Core 2, which is the appropriate page for the processors code-named "Conroe", "Merom", "Allendale", etc..

However, grouping by family ID is wrong; the Intel Core Microarchitecture is sufficiently different from the P6 and Pentium M microarchitectures that the Core Microarchitecture processors shouldn't just be grouped with the PII and PIII. Guy Harris 19:42, 14 July 2006 (UTC)[reply]

No such thing as "P8"[edit]

Intel officially calls it the Next Generation Microarchitecture. Dan100 (Talk) 10:49, 13 December 2005 (UTC)[reply]

I'd then propose we leave the article as is, the architecture article being INGM (with Intel P8 redirected here) and Conroe a seperate article. --Defsac 03:34, 17 December 2005 (UTC)[reply]

Thing is, at this point, there's virtually no information about Conroe that's not covered by NGMA. There simply aren't enough details on Conroe, at this moment, to warrant a separate article. I propose that we re-create the Conroe article only when both a final name and details on the available models are released. Jgp 03:56, 17 December 2005 (UTC)[reply]
I agree with Jgp. All information about Conroe are covered by NGMA. When more information will be available, we could create some new articles about each processor (Merom, Conroe, Woodcrest) whose links will be available in the NGMA article. Just like NetBurst article which has the links of all NetBurst processors. kostas213 19:13, 26 January 2006 (UTC)[reply]

FSB for Merom is 1066 MHz?[edit]

I don't think that Merom's FSB is 1066 MHz, but it is 667 MHz, just like the FSB of Core Duo (Yonah) processor. It is known that Merom will make use of the same chipset (945) as Core Duo. So the FSB will be 667 MHz, as I think. It is also should be mentioned that Merom - Conroe - Woodcrest are 4-issue cores.

You're right. I have, however, heard that a second wave of Meroms will launch in early 2007, supporting an 800 MHz FSB. I've corrected the FSB data, and I've also switched MHz over to MT/s, due to conflicts on other pages regarding what constitutes FSB speed. Jgp 22:50, 25 January 2006 (UTC)[reply]

NGMA cores are 4-issue wide.[edit]

I have added that the new cores will be 4-issue. I think that this fact is one of the most important characteristics of the new architecture. I have also mentioned that previous architectures (P6, P6-Banias, NetBurst) made use of 3-issue cores. --kostas213 19:02, 26 January 2006 (UTC)[reply]

Looks good, the info as put by Intel is "A four-issue-wide, 14-stage main pipeline" Someone may also want to add the info "Shared on-chip L2 cache — The dual-core Core processors will feature a single, unified L2 cache that should allow for efficient sharing of data between the processor cores with no need for external bus traffic for cache coherency protocol traffic between the cores. Rattner said that there would be no partitioning of the L2 cache between cores, and in the event that one core should shut itself down to save power during a period of inactivity, the other core could make use of the full L2 cache if needed."

Release dates[edit]

Does anybody know when Intel plans to release the 3 new processors to the market? If yes, I think it would be a useful addition to the article. aditsu 21:23, 13 March 2006 (UTC) (shaking with anxiety)[reply]

I found several articles that say the 3 processors are officially scheduled for Q3 (July - September), most likely in this order: Woodcrest first, then Conroe, then Merom. Some say Conroe (the one I'm most interested in) is "expected" to be delivered in July, while others say August or even later; but it looks like mere speculation at this time. Example articles: [1] [2] [3]. If you find anything worthy to be included in the main article here, feel free to do that. aditsu 08:10, 27 April 2006 (UTC)[reply]


I have added the release dates as they have now been confirmed officially by Intel.
http://dailytech.com/article.aspx?newsid=2015
MacGyver 13:12, 3 May 2006 (UTC)[reply]


Added the dailytech.com article to the references so it was more easily accessible and verifiable. 23:37, 6 May 2006 (UTC)

Wikipedia is not a Crystal Ball[edit]

Can someone explain to me why much of this article does not violate WP:NOT#Wikipedia is not a crystal ball? It says "Wikipedia is not a collection of unverifiable speculation. All articles about anticipated events must be verifiable ...". I mean, the processor line is interesting, of course, but why not wait until it actually comes out instead of speculating? -- Gnetwerker 07:40, 20 March 2006 (UTC)[reply]

The additional Links are not enough to be considered verifiable? Selfexiled 09:42, 23 March 2006 (UTC)[reply]

Seriously, this article is of interest to a lot of people. It's the first I've read about it... and it's not like it's trivial or isn't going to happen. Not like making a page about the next Korn concert or whatever, which is what the "not a crystal ball" clause is supposed to cover.

Neutrality[edit]

Why is this page marked as "questionable neutrality"? What is the complaint?

Are there genuine 3GHz Clovertown parts?[edit]

I am aware of the Mac Pros containing quad-core 3GHz processors, but aren't they just overclocked Clovertowns? --Masud 20:44, 4 April 2007 (UTC)[reply]

I have found the answer: according to Intel's Bill Kircos[4] these are really 3GHz. --Masud 11:47, 6 April 2007 (UTC)[reply]

Quad Core?[edit]

Aren't the cloverotwn's and kentsfield quad core yet in the server section in the table they are all listed as having 2 cores. Could someone clear this up? 203.214.6.247 08:54, 22 April 2007 (UTC)[reply]

Oops, you're quite right. When I did the overhaul and created the tables, I forgot to do that. I've done it now, thanks for the reminder. --Masud 15:32, 22 April 2007 (UTC)[reply]

Xeon 3040/3050 allendale?[edit]

Did intel change to the Allendale core on the Xeon 3040s/3050s recently? Since release they've been Conroes with half of their L2 cache disabled, basically e6300 and e6400 chips. The article states that they are Allendale core, I did not change it because quite frankly I don't know. The hardcore icon the sandman 22:11, 25 May 2007 (UTC)[reply]

Article title[edit]

The following discussion is closed. Please do not modify it. Subsequent comments should be made in a new section. A summary of the conclusions reached follows.
The latest result of these previous discussions was to move the article to Intel Core (microarchitecture) (done with this edit). Trevj (talk) 20:08, 28 June 2011 (UTC)[reply]

Page move[edit]

Since "Microarchitecture" isn't part of the official name, why rename the article to Intel Core microarchitecture instead of Intel Core (microarchitecture). The latter is more conventional. jgp TC 00:25, 13 September 2006 (UTC)[reply]

Sounds reasonable. I was just addressing WP:NC's capitalization guideline but the expert editors here can ponder that avenue as well. I'd consider whether people ever refer to the microarchitecture as simply "Intel Core". It appears that term would always refer to something else but I could be wrong. —Wknight94 (talk) 00:51, 13 September 2006 (UTC)[reply]

Rename article?[edit]

To bring this article in line with Nehalem (CPU architecture) and Gesher (CPU architecture), should this article be renamed to Intel Core (CPU architecture)? --Masud 21:38, 22 April 2007 (UTC)[reply]

I'm not sure that would be consistent because NetBurst has nothing in brackets and neither does Intel P6 and we can't get rid of the microarchitecture part either because that would cause confusion with Intel Core.--Sat84 11:53, 23 April 2007 (UTC)[reply]
Hmmm... but don't we normally have things in brackets when we distinguish between two things that are named the same thing? For example Fight Club (film) and Fight Club (video game)? In this case, we have the processor and the architecture, both called the same thing: Intel Core and so we need the distinguishing. Similarly, there will be a processor called Nehalem but the term is also used to describe the architecture. --Masud 12:46, 23 April 2007 (UTC)[reply]
Seems reasonable but then we would have to change Intel Core to Intel Core (CPU) to be consistent or would we leave that alone?--Sat84 13:12, 24 April 2007 (UTC)[reply]
I should think the rename of that article is in order too. --Masud 15:54, 24 April 2007 (UTC)[reply]
And irritatingly enough, the Intel Core (CPU) isn't even of the Intel Core (CPU architecture)! --Masud 16:00, 24 April 2007 (UTC)[reply]
Changing it would make sense & I'd support it. Cooldude7273 01:01, 25 April 2007 (UTC)[reply]

And so it was done. --Masud 00:38, 27 April 2007 (UTC)[reply]

Rename article (2)?[edit]

Shouldn't the article be renamaed to "Intel Core (microarchitecture)" (together with the Nehalem (CPU architecture) and Gesher (CPU architecture) articles) to avoid using the word "architecture" for microarchitecture (hardware) and instruction set (software) possibly confusing a bit?

I don't see the confusion here, explain it a little bit better please.--Sat84 13:36, 10 August 2007 (UTC)[reply]
I suggested on Talk:Nehalem (CPU architecture) that we rename Intel Core (CPU architecture), Nehalem (CPU architecture), and Sandy Bridge (CPU architecture) to "Intel Core (CPU microarchitecture)", "Nehalem (CPU microarchitecture)", and "Sandy Bridge (CPU microarchitecture)". My reason is that the terms "architecture" and "microarchitecture" refer to different things. "Architecture" is for the overall design of the processor (as in the ISA), such as x86, POWER, Alpha, SPARC, etc. Microarchitecture, on the other hand, refers to the specific implementation of the design. CPUs with different architectures are not compatible, but those with different microarchitectures are compatible. That's my idea, what do you think? Imperator3733 23:37, 24 September 2007 (UTC)[reply]
Sounds good to me and I'd agree with that. --Masud 15:13, 25 September 2007 (UTC)[reply]
But now the the Article called "Core" it has to include the Yona-Processor as well, doesnt it ? —Preceding unsigned comment added by 192.109.190.88 (talk) 08:42, 26 September 2007 (UTC)[reply]
Yonah does not use the Core microarchitecture, it is already mentioned on Intel Core, and this naming change would have no impact w.r.t. Yonah. This would be a more technically correct way to title the articles. I do have 2 notes about this change though: first that 'microarchitecture' is a pain to spell (good use of redirects and some copy-paste can save one from actually typing it out, though); second that the word "CPU" is no longer necessary if this change is made, as there is no ambiguity about what sort of microarchitecture the titles might be refering to. AFAIK there are no other definitions in common use. — Aluvus t/c 05:16, 28 September 2007 (UTC)[reply]
So how does renaming the articles to Intel Core (microarchitecture), Nehalem (microarchitecture), and Sandy Bridge (microarchitecture) sound? Another possibility would be to have "Intel" in all the names (making the naming more consistent -- i.e. Intel Nehalem (microarchitecture) and Intel Sandy Bridge (microarchitecture). If we do that I would suggest making the change to other uArch pages (i.e. NetBurst to Intel NetBurst (microarchitecture), Intel P6 to Intel P6 (microarchitecture, etc). So, what do you think? I'll give this a week for comments. If the response is favorable, I (or someone else) will/can rename them. If there is no response, I'll probably wait a bit longer. -- Imperator3733 22:02, 10 October 2007 (UTC)[reply]
As no one has responded to this proposal, I am going to give the idea one more week. I am adding this proposal to the Talk:Nehalem (CPU architecture) and Talk:Sandy Bridge (CPU architecture). -- Imperator3733 00:23, 16 October 2007 (UTC)[reply]
I think Nehalem (microarchitecture) is better than Intel Nehalem (microarchitecture), as Nehalem is just a codename and we don't have the official name for it. We can rename it when (and if) its commercial name is announced. Incidentally, what does Intel use on their official literature; Intel Core or Core? If they only use Core, then this article should be renamed to Core (microarchitecture).
Also taking into account Aluvus's concerns, what about marchitecture? I know it's not a well-known abbreviation, so perhaps it's not a great idea.
--Masud 23:05, 18 October 2007 (UTC)[reply]
In Intel's Core 2 Duo desktop product brief [5], they call it the "Intel® Core® microarchitecture" (page 1, 2nd column, top line).
You're right about "marchitecture" not being very well known -- I think I've seen it maybe once or twice in approx. 3 years. The abbreviation I know and use is "μArch" or "uArch". -- Imperator3733 23:51, 18 October 2007 (UTC)[reply]
The pages have now been renamed. See Intel Core (microarchitecture), Nehalem (microarchitecture), and Sandy Bridge (microarchitecture) -- Imperator3733 18:05, 24 October 2007 (UTC)[reply]
The discussion above is closed. Please do not modify it. Subsequent comments should be made on the appropriate discussion page. No further edits should be made to this discussion.

Processor tables[edit]

Why does this page have processor tables on it? Isn't that stuff already at List of Intel Core 2 microprocessors and List of future Intel Core 2 microprocessors? It seems redundant to me. -- Imperator3733 23:29, 24 October 2007 (UTC)[reply]

It gives an overview on all the processors based on Core microarchitecture, including Celeron M & Celeron, Pentium Dual-Core, and Xeon variants, all on a single page.Coldpower27 02:17, 25 October 2007 (UTC)[reply]
It just seems that it takes up most of the page. -- Imperator3733 03:44, 25 October 2007 (UTC)[reply]
I initially added the processor tables. This is what it used to look like before I added them http://en.wikipedia.org/w/index.php?title=Intel_Core_%28microarchitecture%29&oldid=122474374. Given that I added them, of course I'm going to think they are a good idea, but here are the reasons why:
  • They provide a handy "at-a-glance" way to compare and contrast all the processors. Even for those of us who keep up with the Intel processor codenames, they are still quite confusing, and these tables help to a great degree. I know I have come to this page several times to quickly find out what the details of certain processors are by model number.
  • They are better than the list pages in the sense that one can quickly compare processors of the same type.The fact that there are only performance details (as opposed to the list pages which have sSpec number, multiplier, release date, price etc.) also aids in quick comparison
  • They are a substantial improvement upon the older lists of processors
  • They provide a handy way to view upcoming processor technology
The possible downsides I can think of are:
  1. The article is becoming too long
  2. Maintaining consistency across Wikipedia of other CPU architectures is difficult/impossible
  3. Keeping the tables up-to-date is too much of a demand on Wikipedians
  4. Redundancy
The responses would be:
  1. This is a genuine issue that needs to be taken into account. I personally think that the tables are useful to visitors of the page, especially as newer processors come out.
  2. This is also a genuine issue. As a comparison, AMD K10 article has a nice balance of μarch details and specifies the naming scheme, but as far as I know, Intel does not follow any logical numbering scheme (except for higher = better).
  3. Initially I was copying all the data from the list articles, but as the article grew in prominence there are plenty of Wikipedians doing this task.
  4. While the tables present essentially the same (if not less) information as the list articles, the presentation is entirely different, and in my opinion, this difference in presentation is enough to warrant the inclusion of the tables.
--Masud 11:34, 25 October 2007 (UTC)[reply]
What is your policy on ordering of the processors? I think I'd go either with "dualcore/quadcore/extreme" as primary key, and architecture (ie, Conroe (-based), Wolfdale (-based)) as secondary key, or perhaps the other way around. 80.101.113.45 (talk) 13:10, 12 August 2008 (UTC)[reply]

Intel ARK[edit]

In case you didn't know, Intel has their ARK (Automated Relational Knowledgebase) in beta. It lists all of their processors and all their details. See http://arstechnica.com/news.ars/post/20071107-intels-new-ark-is-lifeboat-for-journalists-chip-junkies.html for more details.

Masud 06:16, 9 November 2007 (UTC)[reply]

Sweet! That sounds very interesting. -- Imperator3733 18:49, 9 November 2007 (UTC)[reply]

Intel ARK --Ramu50 (talk) 00:01, 18 July 2008 (UTC)[reply]

Processor roadmaps[edit]

I've started a discussion on the processor roadmap graphics over at Talk:Nehalem (microarchitecture)#Processor roadmaps. Please take a look and make a comment if you have any thoughts. Thank you. -- Imperator3733 (talk) 15:06, 11 June 2008 (UTC)[reply]

List of steppings?[edit]

The processor table seems useful, but what I'd rather like to see is a table that shows the relation between all the steppings and how they are used.

List of 65nm Intel Core steppings:

Mobile (Merom) Desktop (Conroe) Desktop (Kentsfield) Server (Woodcrest, Tigerton, Clovertown)
Stepping Released Area CPUID L2 Cache Max Clock Celeron Pentium Core 2 Celeron Pentium Core 2 Xeon Core 2 Xeon Xeon
B2 Jul 2006 143mm² 06F6 4MB 2.93GHz M5xx T5000 T7000 L7000 E6000 X6000 3000 5100
B3 Nov 2006 143mm² 06F7 4MB 3.00GHz Q6000 QX6000 3200 5300
L2 Jan 2007 111mm² 06F2 2MB 2.13GHz T5000 U7000 E2000 E4000 E6000 3000
E1 May 2007 143mm² 06FA 4MB 2.80GHz M5xx T7000 L7000 X7000
G0 Apr 2007 143mm² 06FB 4MB 3.00GHz T7000 L7000 X7000 E4000 E6000 Q6000 3000 Q6000 QX6000 3200 5100 5300 7200 7300
M0 Jul 2007 111mm² 06FD 2MB 2.40GHz 5xx T1000 T2000 T5000 T7000 U7000 E1000 E2000 E4000
A1 Jun 2007 81mm² 10661 1MB 2.20GHz M5xx U2000 220 4x0

List of 45nm Intel Core steppings:

Mobile (Penryn) Desktop (Wolfdale) Desktop (Yorkfield) Server (Harpertown) Server (Dunnington)
Stepping Released Area CPUID L2 Cache Max Clock Celeron Core 2 Pentium Core 2 Xeon Core 2 Xeon Xeon
C0 Nov2007 107mm 10676 6MB 3.00GHz T9000 P9000 SP9000 SL9000 X9000 E8000 3100 QX9000 5200 5400
M0 Mar2008 82mm 10676 3MB 2.40GHz 7xx SU3000 P7000 P8000 T8000 SU9000 E5000 E7000
C1 Mar2008 107mm 10677 6MB 3.20GHz Q9000 QX9000 3300
M1 Mar2008 82mm 10677 3MB 2.50GHz Q8000 Q9000 3300
E0 Aug2008 107mm 1067A 6MB 3.33GHz T9000 P9000 Q9000 QX9000 E8000 3100 Q9000 Q9000S QX9000 3300 5200 5400
R0 Aug2008 82mm 1067A 3MB 2.93GHz 7xx T6000 P8000 SU9000 E5000 E7000 Q8000 Q8000S Q9000 Q9000S 3300
A1 Sep2008 ?? 106D1 3MB 2.67GHz 7400


I think that looks pretty cool. Part of the issue though is explaining what this means to the average reader of the article. While most readers would be familiar with processor model names, and things like no. of cores etc., we might need an explanatory paragraph preceding these tables.
I don't think it clutters the article, as I find the information thus presented to be quite interesting. However, others may disagree. Any further opinions?
--Masudr (talk) 15:27, 28 January 2009 (UTC)[reply]

Superscalar[edit]

The article says: "Core's execution unit is 4 issues wide, compared to the 3-issue cores of P6, P-M (Banias, Dothan, and Yonah), and NetBurst microarchitectures."

This sentence does not make any sense. There is no "execution unit". There are multiple execution units, a combination of ALUs, AGUs and FPUs (and perhaps some special purpose units on the side). These execution units are fed with instructions dispatched from something such as a reserve station. The "four-issue" refers to the number of micro-ops (or whatever they are called these days) that are sent to the reserve station. The reserve station itself can dispatch more instructions to the execution units than the number of instructions sent to it.

The sentence should say something along the lines of: The Core microarchitecture is a four-way superscalar design, compared to the three-way superscalar P6.

Before someone rushes to update the article, my comments are based on the P6 microarchitecture. The Core microarchitecture may be completely different, I don't know, but the sentence needs to be fixed. Rilak (talk) 12:09, 13 March 2009 (UTC)[reply]

Is it x86, after all?[edit]

The intro does mention Pentium so I am assuming the instruction set is x86 based, but is it so? This should be mentioned/explained in the intro (unlike most other technical details in this article, this is important for the "regular" users trying to find proper compiler options when transfering codes between different machines!) Thanks. —Preceding unsigned comment added by 128.97.82.220 (talk) 02:03, 3 December 2009 (UTC)[reply]

Interoperability[edit]

Some mention of what these things can go into would be extremely helpful! For example - can I pull out my Socket 604 chip, and substitute in any other socket 604; and if not - is there some way to figure out from what I'm currently using, what other ones will work? 203.45.103.88 (talk) 05:23, 28 March 2010 (UTC)[reply]

This issue is normally addressed in the articles on individual products and sockets. It can be a surprisingly complex issue, and cuts across microarchitectures anyway (Netburst and Core products are both available on LGA 775, for example). — Aluvus t/c 20:27, 28 March 2010 (UTC)[reply]

Inconsistency between Wikipedia pages[edit]

List of Intel Core 2 microprocessors says that the Core 2 Quad Q9550S has a 2×6MB L2 cache, while this page says it's a (implied single) 12MB L2. That's a significant difference -- the pair of cores that share an LS will communicate faster than the ones using separate L2 caches. The processor table suggested above has less duplication of information and thus reduces the chances of inconsistency. Guy Macon 20:32, 21 April 2010 (UTC)[reply]

IntelProcessorRoadmap.svg needs small update[edit]

According to http://en.wikipedia.org/wiki/Sandy_Bridge were Sandy Bridge mainstream processors launched earlier this year, so 'Sandy Bridge' in the technology roadmap figure (IntelProcessorRoadmap.svg) should be black, not blue (as it is not a future technology any more). — Preceding unsigned comment added by Andre.holzner (talk • contribs) 11:46, 21 February 2011 (UTC)[reply]

A comprehensive authoritative summary of recent Intel microarchitecture[edit]

This link should be added as a reference/external link and the information can be used to update and refresh the data in the article: Intel Processor Identification with CPUID — Preceding unsigned comment added by Husmousa (talk • contribs) 21:45, 4 December 2011 (UTC)[reply]

Israel's role in Core design[edit]

The last sentence and source in the intro (ie. "The Core microarchitecture was designed by Israel's Intel Israel (IDC) team...") are not coherent. The article states that Intel Israel were responsible for the Core 2 Duo, but nothing about earlier iterations etc. It should be changed to reflect the source, or better sources found for the claim.60.242.39.220 (talk) 13:57, 15 April 2012 (UTC)[reply]

Is Dunnington model correct[edit]

Two places on the page describe Dunnington as model 30, and two give a CPUID value as 0x106DX but D=13 so 0x106DX would be model 29 not model 30. Which is it? — Preceding unsigned comment added by 94.245.127.15 (talk) 12:30, 28 May 2012 (UTC)[reply]

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