WDC 65C02

The Western Design Center WDC 65C02 microprocessor is an upgraded CMOS version of the popular NMOS-based MOS Technology 6502 8-bit CPU—the CMOS redesign being made by Bill Mensch of the Western Design Center (WDC). Over various periods of time, the 65C02 has been second-sourced by NCR, GTE, Rockwell, Synertek and Sanyo.

WDC 65C02 microprocessor in a PDIP-40 package.

Introduction and features

The W65C02S is the Western Design Center's version of the 65C02 microprocessor. The "S" designation indicates that the part has a fully static core which allows the primary (Ø2) clock to be slowed down or fully stopped in either the high or low state with no loss of data. Typical microprocessors not implemented in CMOS have dynamic cores and will lose their internal register contents (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.

WDC 65C02 registers

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers   A Accumulator Index registers   X X index   Y Y index 0 0 0 0 0 0 0 1 SP Stack Pointer Program counter PC Program Counter Status register   N V - B D I Z C P Processor flags

The W65C02S is a low-power general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The variable length instruction set and manually optimized core size are intended to make the W65C02S well suited for low power system-on-chip (SoC) designs.

WDC makes a Verilog hardware description model available for designing the 65C02 core into ASICs and FPGAs. As is common in the semiconductor industry, the company also provides a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.

General logic features

• 8-bit data bus
• 16-bit address bus (providing an address space of 64K bytes)
• 8-bit arithmetic logic unit (ALU)
• 8-bit processor registers:
  • accumulator
  • stack pointer
  • index registers
  • status register
• 16-bit program counter
• 69 instructions, implemented by 212 operation codes
• 16 addressing modes, including zero page addressing

Logic specifics

• Vector Pull (VPB) output indicates when interrupt vectors are being addressed
• WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and enable synchronization with external events

Electrical features

• Supply voltage specified at 1.71 V to 5.25 V
• Current consumption (core) of 0.15 and 1.5 mA per MHz at 1.89 V and 5.25 V respectively
• Variable length instruction set, enabling code size optimization over fixed length instruction set processors, results in power savings
• Fully static circuitry allows stopping the clock to conserve power

The WDC 65C02 can run at any supply voltage (V_DD) between 1.8 and 5 volts (±5%). There are not different chips for different logic supply voltages. The data sheet shows graphs of how various parameters (e.g. IDD, Fmax) change with VDD, and tables showing their values at commonly used VDD values (1.8, 2.5, 3.0, 3.3, 5.0 V ±5%).

The WDC6502 data sheet table 6.3 shows AC characteristics at 5V/14 MHz, 3.3V/8 MHz, 3V/8 MHz, 2.5V/4 MHz, and 1.8V/2 MHz. This may be left over from an earlier data sheet, because the graph in figure 6.2 indicates that typical devices run over 18 MHz at 4V, and 6 MHz at 1.8V.

The -14 suffix should not be taken as a 14 MHz hard limit. The WDC6502 may well run at convenient clocks such as 13.5 MHz (digital SDTV luma sampling rate), 14.31818.. MHz (NTSC colour carrier × 4), 14.75 MHz (PAL square pixels), 14.7456 (baud rate crystal), 16 MHz and so on. However, the minimum VDD value rises accordingly.

Bill Mensch pointed out that Fmax depends on off-chip factors such as the capacitive load on the pins. Minimising load by using short signal tracks and fewest devices helps raise Fmax. The PLCC package has less pin-to-pin capacitance than the DIP-40 package.

Comparison with the MOS 6502

Instruction set

The 65C02 shares its predecessor's 8-bit instruction set architecture and 16-bit memory address space $0000 to $FFFF allowing access to a total memory map of 64K. "Zero Page" spans $0000 to $00FF. "Page 1" spans memory address space $0100 to $01FF and is dedicated for the stack. On this processor the stack grows downwards with the stack pointer starting at $01FF and decrementing as the stack grows.

It adds a number of improvements and documented opcodes, the most useful being instructions that can push or pull the X and Y index registers to/from the stack. Undefined opcodes have been converted into NOPs, although of varying instruction lengths.

Significantly, the defective "indirect jump page wrap" instruction (JMP (<ADDR>), where <ADDR> straddles a memory page boundary) has been fixed, eliminating a constant source of trouble for unwary assembly language programmers. This instruction has also been enhanced with .X register indexing, making it possible to code JMP (<ADDR>,X), enabling the development of a simple jump table management methodology.

Some variants of the 65C02 (including the WDC W65C02S and the Rockwell R65C00 family) feature individual bit manipulation operations (RMB, SMB, BBR and BBS). The 65SC02 was also available, which lacked these operations.

Status register

Other problems with the 6502, fixed in the 65C02, relate to its program status register, which contains eight system flags. Some flags are set or reset under program control. Others reflect the status of the machine after arithmetic or bit manipulation instructions.

6502 status flags, with meanings when set:

N	--	Negative result
V	--	Sign bit overflow
1	--	Undefined (always set)
B	--	Break flag (set by BRK instruction)
D	--	Decimal mode enabled
I	--	IRQ disabled
Z	--	Zero result
C	--	Arithmetic carry (borrow)

In all NMOS logic forms of the 6502, the decimal flag (D flag) is not initialized to a known state following reset or when an interrupt is processed, which may lead to arbitrary behavior. This forces 6502 programmers to use the CLD instruction early in the reset handler code (it is generally the second instruction executed after SEI), as well as in the front end of the interrupt handler. The 65C02 addresses these problems by causing the D flag to be cleared at reset or upon receipt of an interrupt (after the status register is pushed onto the stack).

Also, in NMOS 6502s, the N flag is invalid when the processor is operating in decimal mode. The 65C02 fixes this problem (at the cost of an additional clock cycle), and thus increases the usefulness of decimal mode.

65SC02

The 65SC02 is a variant of the WDC 65C02 with additional instructions. And it's the base for the HuC6280 by NEC used in their video game console TG-16 (PC-Engine) and the 65CE02 which is used in the MOS Technology 4510 CPU core which in turn is used in the Commodore 65 product of 1990. The bit operation capability of the 6502's and the 65C02 were poor which impeded bit-oriented compression or decompression algorithms like Huffman coding and so the 65SC02 got new bit operations.

Notable uses of the 65C02

Home computers

• Apple IIc portable improved Apple II, by Apple Computer (1.023 MHz)
• Apple Enhanced IIe by Apple Computer (1.023 MHz)
• BBC Master home/educational computer, by Acorn Computers Ltd (2 MHz 65SC12 plus optional 4 MHz 65C102 second processor)
• Replica I by Briel Computers, a replica of the Apple I hobbyist computer (1 MHz)
• Laser 128 series clones of Apple II

Video game consoles

• Atari Lynx handheld (65SC02 @ ~4 MHz)
• NEC PC Engine aka TurboGrafx (HuC6280 @ 7.16 MHz)
• GameKing handhelds (6 MHz), by Time Top
• Watara Supervision handhelds (65SC02 @ 4 MHz)

Other products

• TurboMaster accelerator cartridge for the Commodore 64 home computer (65C02 @ 4.09 MHz)
• many dedicated chess computer i.e.: Mephisto MMV, Novag Super Constellation, Fidelity Elite and many more (4–20 MHz)

See also

• Interrupts in 65xx processors

External links

• W65C02S 8–bit Microprocessor – PDF datasheet at WDC's 65xx.com website
• The 6502/65C02/65C816 Instruction Set Decoded – From Neil Parker's Apple II page
• CPU World