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transistor is not a device
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==Classification==
==Classification==
[[File: Through-Silicon Via Flavours.svg|thumb|upright=1.36|Visualizing via-first, via-middle and via-last TSVs]]
[[File: Through-Silicon Via Flavours.svg|thumb|upright=1.36|Visualizing via-first, via-middle and via-last TSVs]]
Dictated by the manufacturing process, there exist three different types of TSVs: ''via-first TSVs'' are fabricated before the individual devices ([[transistor]]s, [[capacitor]]s, [[resistor]]s, etc.) are patterned ([[front end of line]], FEOL), ''via-middle TSVs'' are fabricated after the individual devices are patterned but before the metal layers ([[Back end of line|back-end-of-line]], BEOL), and ''via-last TSVs'' are fabricated after (or during) the BEOL process.<ref>{{cite book |title=2009 International Technology Roadmap for Semiconductors (ITRS) |url=https://www.semiconductors.org/resources/2009-international-technology-roadmap-for-semiconductors-itrs/ |pages=4–5 }}</ref><ref name=3D>{{cite journal |last1=Knechtel |first1=Johann |last2=Sinanoglu |first2=Ozgur |last3=Elfadel |first3=Ibrahim (Abe) M. |last4=Lienig |first4=Jens |last5=Sze |first5=Cliff C. N. |title=Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration |journal=IPSJ Transactions on System LSI Design Methodology |date=2017 |volume=10 |pages=45–62 |doi=10.2197/ipsjtsldm.10.45 |doi-access=free }}</ref> Via-middle TSVs are currently a popular option for advanced [[3D IC]]s as well as for [[interposer]] stacks.<ref name=3D /><ref>{{cite journal |last1=Beyne |first1=Eric |title=The 3-D Interconnect Technology Landscape |journal=IEEE Design & Test |date=June 2016 |volume=33 |issue=3 |pages=8–20 |doi=10.1109/mdat.2016.2544837 |s2cid=29564868 }}</ref>
Dictated by the manufacturing process, there exist three different types of TSVs: ''via-first TSVs'' are fabricated before the individual component ([[transistor]]s, [[capacitor]]s, [[resistor]]s, etc.) are patterned ([[front end of line]], FEOL), ''via-middle TSVs'' are fabricated after the individual component are patterned but before the metal layers ([[Back end of line|back-end-of-line]], BEOL), and ''via-last TSVs'' are fabricated after (or during) the BEOL process.<ref>{{cite book |title=2009 International Technology Roadmap for Semiconductors (ITRS) |url=https://www.semiconductors.org/resources/2009-international-technology-roadmap-for-semiconductors-itrs/ |pages=4–5 }}</ref><ref name=3D>{{cite journal |last1=Knechtel |first1=Johann |last2=Sinanoglu |first2=Ozgur |last3=Elfadel |first3=Ibrahim (Abe) M. |last4=Lienig |first4=Jens |last5=Sze |first5=Cliff C. N. |title=Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration |journal=IPSJ Transactions on System LSI Design Methodology |date=2017 |volume=10 |pages=45–62 |doi=10.2197/ipsjtsldm.10.45 |doi-access=free }}</ref> Via-middle TSVs are currently a popular option for advanced [[3D IC]]s as well as for [[interposer]] stacks.<ref name=3D /><ref>{{cite journal |last1=Beyne |first1=Eric |title=The 3-D Interconnect Technology Landscape |journal=IEEE Design & Test |date=June 2016 |volume=33 |issue=3 |pages=8–20 |doi=10.1109/mdat.2016.2544837 |s2cid=29564868 }}</ref>


TSVs through the [[front end of line]] (FEOL) have to be carefully accounted for during the [[Electronic design automation|EDA]] and manufacturing phases. That is because TSVs induce [[Stress (mechanics)|thermo-mechanical stress]] in the FEOL layer, thereby impacting the [[Transistor–transistor logic|transistor]] behaviour.<ref>{{cite book |doi=10.1007/978-1-4419-9542-1 |title=Design for High Performance, Low Power, and Reliable 3D Integrated Circuits |year=2013 |last1=Lim |first1=Sung Kyu |isbn=978-1-4419-9541-4 }}</ref>
TSVs through the [[front end of line]] (FEOL) have to be carefully accounted for during the [[Electronic design automation|EDA]] and manufacturing phases. That is because TSVs induce [[Stress (mechanics)|thermo-mechanical stress]] in the FEOL layer, thereby impacting the [[Transistor–transistor logic|transistor]] behaviour.<ref>{{cite book |doi=10.1007/978-1-4419-9542-1 |title=Design for High Performance, Low Power, and Reliable 3D Integrated Circuits |year=2013 |last1=Lim |first1=Sung Kyu |isbn=978-1-4419-9541-4 }}</ref>

Revision as of 10:31, 28 July 2022

TSVs used by stacked DRAM-dice in combination with a High Bandwidth Memory (HBM) interface

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.

Classification

Visualizing via-first, via-middle and via-last TSVs

Dictated by the manufacturing process, there exist three different types of TSVs: via-first TSVs are fabricated before the individual component (transistors, capacitors, resistors, etc.) are patterned (front end of line, FEOL), via-middle TSVs are fabricated after the individual component are patterned but before the metal layers (back-end-of-line, BEOL), and via-last TSVs are fabricated after (or during) the BEOL process.[1][2] Via-middle TSVs are currently a popular option for advanced 3D ICs as well as for interposer stacks.[2][3]

TSVs through the front end of line (FEOL) have to be carefully accounted for during the EDA and manufacturing phases. That is because TSVs induce thermo-mechanical stress in the FEOL layer, thereby impacting the transistor behaviour.[4]

Applications

Image sensors

CMOS image sensors (CIS) were among the first applications to adopt TSV(s) in volume manufacturing. In initial CIS applications, TSVs were formed on the backside of the image sensor wafer to form interconnects, eliminate wire bonds, and allow for reduced form factor and higher-density interconnects. Chip stacking came about only with the advent of backside illuminated (BSI) CIS, and involved reversing the order of the lens, circuitry, and photodiode from traditional front-side illumination so that the light coming through the lens first hits the photodiode and then the circuitry. This was accomplished by flipping the photodiode wafer, thinning the backside, and then bonding it on top of the readout layer using a direct oxide bond, with TSVs as interconnects around the perimeter.[5]

3D packages

A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space and/or have greater connectivity. An alternate type of 3D package can be found in IBM's Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, TSVs replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking).

3D integrated circuits

A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small “footprint.” The different devices in the stack may be heterogeneous, e.g. combining CMOS logic, DRAM and III-V materials into a single IC. In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation. The Wide I/O 3D DRAM memory standard (JEDEC JESD229) includes TSV in the design.[6]

History

Further information: Three-dimensional integrated circuit § History

The origins of the TSV concept can be traced back to William Shockley's patent "Semiconductive Wafer and Method of Making the Same" filed in 1958 and granted in 1962,[7][8] which was further developed by IBM researchers Merlin Smith and Emanuel Stern with their patent "Methods of Making Thru-Connections in Semiconductor Wafers" filed in 1964 and granted in 1967,[9][10] the latter describing a method for etching a hole through silicon.[11] TSV was not originally designed for 3D integration, but the first 3D chips based on TSV were invented later in the 1980s.[12]

The first three-dimensional integrated circuit (3D IC) stacked chips fabricated with a TSV process were invented in 1980s Japan. Hitachi filed a Japanese patent in 1983, followed by Fujitsu in 1984. In 1986, Fujitsu filed a Japanese patent describing a stacked chip structure using TSV.[13] In 1989, Mitsumasa Koyonagi of Tohoku University pioneered the technique of wafer-to-wafer bonding with TSV, which he used to fabricate a 3D LSI chip in 1989.[13][14][15] In 1999, the Association of Super-Advanced Electronics Technologies (ASET) in Japan began funding the development of 3D IC chips using TSV technology, called the "R&D on High Density Electronic System Integration Technology" project.[13][16] The Koyanagi Group at Tohoku University used TSV technology to fabricate a three-layer stacked image sensor chip in 1999, a three-layer memory chip in 2000, a three-layer artificial retina chip in 2001, a three-layer microprocessor in 2002, and a ten-layer memory chip in 2005.[14]

The inter-chip via (ICV) method was developed in 1997 by a Fraunhofer–Siemens research team including Peter Ramm, D. Bollmann, R. Braun, R. Buchner, U. Cao-Minh, Manfred Engelhardt and Armin Klumpp.[17] It was a variation of the TSV process, and was later called SLID (solid liquid inter-diffusion) technology.[18]

The term "through-silicon via" (TSV) was coined by Tru-Si Technologies researchers Sergey Savastiouk, O. Siniaguine, and E. Korczynski, who proposed a TSV method for a 3D wafer-level packaging (WLP) solution in 2000.[19] Savastiouk later became the co-founder and CEO of ALLVIA Inc. From the beginning, his vision of the business plan was to create a through silicon interconnect since these would offer significant performance improvements over wire bonds. Savastiouk published two articles on the topic in Solid State Technology, first in January 2000 and again in 2010. The first article “Moore’s Law – The Z Dimension” was published in Solid State Technology magazine in January 2000.[20] This article outlined the roadmap of the TSV development as a transition from 2D chip stacking to wafer level stacking in the future. In one of the sections titled Through Silicon Vias, Dr. Sergey Savastiouk wrote, “Investment in technologies that provide both wafer-level vertical miniaturization (wafer thinning) and preparation for vertical integration (through silicon vias) makes good sense.” He continued, “By removing the arbitrary 2D conceptual barrier associated with Moore’s Law, we can open up a new dimension in ease of design, test, and manufacturing of IC packages. When we need it the most – for portable computing, memory cards, smart cards, cellular phones, and other uses – we can follow Moore’s Law into the Z dimension.” This was the first time the term "through-silicon via" was used in a technical publication.

CMOS image sensors utilising TSV were commercialized by companies including Toshiba, Aptina and STMicroelectronics during 2007–2008, with Toshiba naming their technology "Through Chip Via" (TCV). 3D-stacked random-access memory (RAM) was commercialized by Elpida Memory, which developed the first 8 GB DRAM chip (stacked with four DDR3 SDRAM dies) in September 2009, and released it in June 2011. TSMC announced plans for 3D IC production with TSV technology in January 2010.[21] In 2011, SK Hynix introduced 16 GB DDR3 SDRAM (40 nm class) using TSV technology,[22] Samsung Electronics introduced 3D-stacked 32 GB DDR3 (30 nm class) based on TSV in September, and then Samsung and Micron Technology announced TSV-based Hybrid Memory Cube (HMC) technology in October.[21] SK Hynix manufactured the first High Bandwidth Memory (HBM) chip, based on TSV technology, in 2013.[22]

References

  1. ^ 2009 International Technology Roadmap for Semiconductors (ITRS). pp. 4–5.
  2. ^ a b Knechtel, Johann; Sinanoglu, Ozgur; Elfadel, Ibrahim (Abe) M.; Lienig, Jens; Sze, Cliff C. N. (2017). "Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration". IPSJ Transactions on System LSI Design Methodology. 10: 45–62. doi:10.2197/ipsjtsldm.10.45.
  3. ^ Beyne, Eric (June 2016). "The 3-D Interconnect Technology Landscape". IEEE Design & Test. 33 (3): 8–20. doi:10.1109/mdat.2016.2544837. S2CID 29564868.
  4. ^ Lim, Sung Kyu (2013). Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. doi:10.1007/978-1-4419-9542-1. ISBN 978-1-4419-9541-4.
  5. ^ F. von Trapp, The Future Of Image Sensors is Chip Stacking http://www.3dincites.com/2014/09/future-image-sensors-chip-stacking
  6. ^ Desjardins, E. "JEDEC Publishes Breakthrough Standard for Wide I/O Mobile DRAM". JEDEC. JEDEC. Retrieved 1 December 2014.
  7. ^ J.H. Lau, Who Invented the Through Silicon Via (TSV) and When? 3D InCites, 2010
  8. ^ U.S. patent 3,044,909
  9. ^ Kada, Morihiro (2015). "Research and Development History of Three-Dimensional Integration Technology". Three-Dimensional Integration of Semiconductors. pp. 1–23. doi:10.1007/978-3-319-18675-7_1. ISBN 978-3-319-18674-0.
  10. ^ U.S. patent 3,343,256
  11. ^ Pavlidis, Vasilis F.; Savidis, Ioannis; Friedman, Eby G. (2017). Three-Dimensional Integrated Circuit Design. Newnes. p. 68. ISBN 978-0-12-410484-6.
  12. ^ Lau, John H. (2010). Reliability of RoHS-Compliant 2D and 3D IC Interconnects. McGraw Hill Professional. p. 1. ISBN 978-0-07-175380-7. TSV is the heart of 3-D IC/Si integration and is a more-than-26-year-old technology. Even the TSV (for electrical feed-through) was invented by William Shockley in 1962 (the patent was filed on October 23, 1958), but it was not originally designed for 3-D integration.
  13. ^ a b c Kada, Morihiro (2015). "Research and Development History of Three-Dimensional Integration Technology" (PDF). Three-Dimensional Integration of Semiconductors: Processing, Materials, and Applications. Springer. pp. 8–9. ISBN 978-3-319-18675-7.
  14. ^ a b Fukushima, T.; Tanaka, T.; Koyanagi, Mitsumasa (2007). "Thermal Issues of 3D ICs" (PDF). SEMATECH. Tohoku University. Archived from the original (PDF) on 16 May 2017. Retrieved 16 May 2017.
  15. ^ Tanaka, Tetsu; Lee, Kang Wook; Fukushima, Takafumi; Koyanagi, Mitsumasa (2011). "3D Integration Technology and Heterogeneous Integration". S2CID 62780117. {{cite journal}}: Cite journal requires |journal= (help)
  16. ^ Takahashi, Kenji; Tanida, Kazumasa (2011). "Vertical Interconnection by ASET". Handbook of 3D Integration, Volume 1: Technology and Applications of 3D Integrated Circuits. John Wiley & Sons. p. 339. ISBN 978-3-527-62306-8.
  17. ^ Ramm, P.; Bollmann, D.; Braun, R.; Buchner, R.; Cao-Minh, U.; et al. (November 1997). "Three dimensional metallization for vertically integrated circuits". Microelectronic Engineering. 37–38: 39–47. doi:10.1016/S0167-9317(97)00092-0. S2CID 22232571.
  18. ^ Macchiolo, A.; Andricek, L.; Moser, H. G.; Nisius, R.; Richter, R. H.; Weigell, P. (1 January 2012). "SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades". Physics Procedia. 37: 1009–1015. arXiv:1202.6497. Bibcode:2012PhPro..37.1009M. doi:10.1016/j.phpro.2012.02.444. S2CID 91179768.
  19. ^ Savastionk, S.; Siniaguine, O.; Korczynski, E. (2000). "Thru-silicon vias for 3D WLP". Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507). pp. 206–207. doi:10.1109/ISAPM.2000.869271. ISBN 0-930815-59-9. S2CID 110397071.
  20. ^ Savastiouk, Sergey (January 2000). "Moore's Law in the Z-Direction". Solid State Technology. 43 (1): 84.
  21. ^ a b Kada, Morihiro (2015). "Research and Development History of Three-Dimensional Integration Technology". Three-Dimensional Integration of Semiconductors: Processing, Materials, and Applications. Springer. pp. 15–8. ISBN 978-3-319-18675-7.
  22. ^ a b "History: 2010s". SK Hynix. Retrieved 19 July 2019.
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