OpenRISC: Difference between revisions
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Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC (who also maintain the [http://www.opencores.org/ opencores.org] website) and the BA12, BA14 and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12. Flextronics International and [[Jennic Limited]] manufactured the OpenRISC as part of an [[Application-specific integrated circuit|ASIC]]. |
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC (who also maintain the [http://www.opencores.org/ opencores.org] website) and the BA12, BA14 and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12. Flextronics International and [[Jennic Limited]] manufactured the OpenRISC as part of an [[Application-specific integrated circuit|ASIC]]. |
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More recently [[Cadence Design Systems]] have started using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to [[Accellera]]<ref>[http://www.uvmworld.org/uvm-reference-flow.php UVM Reference Flow], Accellera website (undated).</ref>). |
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{{Expand section|more commercial examples|date=March 2009}} |
{{Expand section|more commercial examples|date=March 2009}} |
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Revision as of 13:43, 30 August 2011
OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support.[1]
A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. The hardware design was released under the GNU Lesser General Public License, while the models and firmware were released under the GNU General Public License. A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups demonstrated ORPSoC and other OR1200 based designs running on FPGA.[2][3]
Implementations
Most implementations are on FPGAs which give the possibility to iterate on the design at the cost of performance. As the OpenRISC 1000 is now considered stable the OpenCores project is trying to build a cost-efficient ASIC with this design to get improved performance[4]. They launched a call for donations in 2011 with the aim to produce the first ASIC in Q1 2012[5].
Commercial implementations
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC (who also maintain the opencores.org website) and the BA12, BA14 and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12. Flextronics International and Jennic Limited manufactured the OpenRISC as part of an ASIC.
More recently Cadence Design Systems have started using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to Accellera[6]).
![[icon]](/wiki/File:Wiki_letter_w_cropped.svg){kind=small} | This section needs expansion with: more commercial examples. You can help by adding to it. (March 2009) |
Toolchain support
The OpenCores community have ported the GNU toolchain to OpenRISC to support development in C. Using this tool chain, newlib, uClibc, Linux and µClinux have also been ported to the processor. Dynalith provides OpenIDEA, a graphical development environment based on this tool chain.
The OR1K project provides an instruction set simulator, or1ksim. The flagship implementation, the OR1200, is an RTL model in Verilog HDL, from which a SystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative set up by Imperas.
See also
References
- ^ Damjan Lampret et al., "OpenRISC 1000 Architecture Manual", Rev 1.3, 15 Nov 2007. Available from the OpenCores website [1]
- ^ Patrick Pelgrims, Tom Tierens and Dries Driessens, "Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGA’s", De Nayer Instituut, Hogeschool voor Wetenschap & Kunst, 2004. Available online [2]
- ^ Xiang Li and Lin Zuo, "Open source embedded platform based on OpenRISC and DE2-70", Masters dissertation, SoC program, KTH, Sweden. Available online [3]
- ^ OpenCores - Call for OpenRISC ASIC donations
- ^ OpenCores donation FAQ
- ^ UVM Reference Flow, Accellera website (undated).
External links
- OpenRISC main project page at the OpenCores Website
- GNU toolchain building guides
- Beyond Semiconductor commercial fabless semiconductor company founded by the developers of OpenRISC
- Dynalith Systems company website.
- Imperas company website.
- Flextronics International company website
- Jennic company website
- ORSoC company website. ORSoC also maintain the opencores.org website.
- Eetimes article