|Computer memory types|
|Early stage NVRAM|
Ferroelectric Field-Effect Transistor (Fe FET), sometimes called "one transistor FeFET" or "1T-FeFET", is a type of field effect transistor that includes a ferroelectric material sandwiched between the gate electrode and source-drain conduction region of the device - permanent electrical field polarisation in the ferroelectric cause this type of device to retain the transistor's state ("on" or "off") in the absence of any electrical bias.
FeFET based devices are used in FeFET memory - a type of single transistor non-volatile memory
Use of a ferrolectric (triglycine sulfate) in a solid state memory was proped by Moll and Tarui in 1963 using a thin film transistor. Further research occurred in the 1960s, but the retention characteristics of the thin film based devices was unsatisfactory. Early field effect transistor based devices used bismuth titanate (Bi4Ti3O12) ferroelectric, or Pb1-xLnxTiO3 (PLT) and related mixed zironconate/titanates (PLZT). In the late 1980 Ferroelectric RAM was developed, using a ferroelectric thin film as capacitor, connected to an addressing FET.
FeFET based memory devices are read using voltages below the coercive voltage for the ferrolectric.
Issues involved in realising a practical FeFET memory device include (as of 2006) : choice of a high permitivity, highly insulating layer between ferroelectric and gate; issues with high remanent polarisation of ferrolectrics; limited retention time (c. a few days, cf required 10 years).
Provided the ferroelectric layer can be scaled accordingly FeFET based memory devices are expected to scale (shrink) as well as MOSFET devices; however a limit of ~20nm laterally may exist (the superparaelectric limit, aka ferroelectric limit). Other challenges to feature shrinks include : reduced film thickness causing additional (undesired) polarisation effects; charge injection; and leakage currents.
Research and development
In 2017 FeFET based non-volatile memory was reported as having been built at 22nm node using FDSOI CMOS (fully depleted silicon on insulator) with hafnium dioxide (HfO2) as the ferroelectric- the smallest FeFET cell size reported was 0.025 μm2, the devices were built as 32Mbit arrays, using set/reset pulses of ~10ns duration at 4.2V - the devices showed endurance of 105 cycles and data retention up to 300C.
As of 2017[update] the startup 'Ferroelelectrc Memory Company' is attempting to develop FeFET memory into a commercial device, based on Hafnium dioxide. The company's technology is claimed to scale to modern process node sizes, and to integrate with contemporary production processes, ie HKMG, and is easily integrable in to conventional CMOS processes, requiring only two additional masks.
- Ferroelectric RAM - RAM that uses a ferrolectric material in the capacitor of a convention DRAM structure
- Park et al. 2016, §1.1.1, p.3.
- Park et al. 2016, §1.1.1, p.4.
- Park et al. 2016, § 1.1.2, p.6.
- Zschech, Ehrenfried; Whelan, Caroline; Mikolajick, Thomas, eds. (2005), Materials for Information Technology: Devices, Interconnects and Packaging, Springer, pp. 157 -
- Dünkel, S. (Dec 2017), "A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond", 2017 IEEE International Electron Devices Meeting (IEDM), doi:10.1109/IEDM.2017.8268425
- Lapedus, Mark (16 Feb 2017), "What Are FeFETs?", semiengineering.com
- Park, Byung-Eun; Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min, eds. (2016), "Ferroelectric-Gate Field Effect Transistor Memories: Device Physics and Applications", Topics in Applied Physics, Springer (131)