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POWER8

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POWER8
General information
Launched2013
Designed byIBM
Performance
Max. CPU clock rate2.5 GHz to 5 GHz
Cache
L1 cache64+32 KB per core
L2 cache512 KB per chiplet
L3 cache8 MB per chiplet
L4 cache16 MB per Centaur
Architecture and classification
Technology node22 nm
Instruction setPower Architecture (Power ISA v.2.07)
Physical specifications
Cores
  • 4, 6, 8, 10 or 12
History
PredecessorPOWER7
SuccessorPOWER9
POWER, PowerPC, and Power ISA architectures
NXP (formerly Freescale and Motorola)
IBM
IBM/Nintendo
Other
Related links
Cancelled in gray, historic in italic

POWER8 is a family of superscalar symmetric multiprocessors based on the Power Architecture, and introduced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER Foundation, which is the first time for such availability of IBM's highest-end processors.[1][2]

Systems based on POWER8 became available from IBM in June 2014.[3] According to Ken King at IBM, systems and POWER8 processor designs made by other OpenPOWER members will be available in early 2015,[4] but TYAN seems to be ready to ship earlier than that, in October 2014.[5]

Design

POWER8 is designed to be a massively multithreaded chip, with each of its cores capable of handling eight hardware threads simultaneously, for a total of 96 threads executed simultaneously on a 12-core chip. The processor makes use of very large amounts of on- and off-chip eDRAM caches, and on-chip memory controllers enable very high bandwidth to memory and system I/O. For most workloads, the chip is said to perform two to three times as fast as its predecessor, the POWER7.[6]

Where previous POWER processors use the GX++ bus for external communication, POWER8 removes this from the design and replaces it with the CAPI port (Coherent Accelerator Processor Interface) that is layered on top of PCI Express 3.0. The CAPI port is used to connect auxiliary specialized processors such as GPUs, ASICs and FPGAs.[7][8] Units attached to the CAPI bus can use the same memory address space as the CPU, thereby reducing the computing path length. At the 2013 ACM/IEEE Supercomputing Conference, IBM and Nvidia announced an engineering partnership to closely couple POWER8 with Nvidia GPUs in future HPC systems,[9] with the first of them announced as the Power Systems S824L.

POWER8 also contains a so-called on-chip controller (OCC), which is a power and thermal management microcontroller based on a PowerPC 405 processor. It has two general-purpose offload engines (GPEs) and 512 KB of embedded static RAM (SRAM), together with the possibility to access the main memory directly, while running an open-source firmware. OCC manages POWER8's operating frequency, voltage, memory bandwidth, and thermal control for both the processor and memory; it can regulate voltages through 1,764 integrated voltage regulators (IVRs) on the fly. Also, the OCC can be programmed to overclock the POWER8 processor, or to lower its power consumption by reducing the operating frequency (which is similar to the configurable TDP found in some of the Intel and AMD processors).[10][11][12][13]

POWER8 comes in 4-, 6-, 8-, 10- and 12-core variants;[14][15] each version is fabricated in a 22 nm silicon on insulator (SOI) process using 15 metal layers. The 12-core version consists of 4.2 billion transistors[16] and is 650 mm2 large while the 6-core version is only 362 mm2 large.[3]

Centaur

The memory controllers on the POWER8 chips are specified to use either DDR3 or DDR4 memory but are designed to be future-proof by being generic memory controllers paired to an external component called Centaur that acts as a memory buffer, L4 cache chip and the actual memory controller. The current Centaur chip is using DDR3 memory, but a future version can use DDR4 or some other memory technology without the need to modify the design of the POWER8 chip itself.

Links between the POWER8 chip and the Centaur are running at 9.6 GB/s each, with 40 ns latency. Centaur contains 16 MB of eDRAM which can be used as L4 cache by the processor. Each POWER8 can be linked to up to eight Centaur chips allowing for up to 1 TB of memory per socket, with an aggregated 128 MB L4 cache and 230 GB/s sustained memory bandwidth in and out of the processor, with a total of 32 DRAM ports and 410 GB/s peak memory bandwidth at the DRAM. Centaur chips are mounted onto DRAM DIMM modules.[1][17][18]

The Centaur chips are fabricated with a process similar to that of the POWER8.

Specifications

The POWER8 core has 64 KB L1 data and 32 KB L1 instruction caches. Each core can issue 10 instructions and dispatch 8 each cycle to 16 Execution Units (EU); 2× Fixed-Point Units (FXU), 2× Load-Store Units (LSU), 2× Instruction Fetch Units (IFU), 4× Floating Point Units (FPU), 2× VMX units, 1× Cryptographic Unit, 1× Decimal Floating Unit (DFU), 1× Condition Register Unit (CRU), and 1× Branch Register Unit (BRU).[17]

It has a larger issue queue with 4×16 entries, improved branch predictors and can handle twice as many cache misses. Each core is eight-way hardware multithreaded and can be dynamically and automatically partitioned to have either one, two, four or all eight threads active.[1] POWER8 also added support for hardware transactional memory.[19][20][21] IBM estimates that each core is 1.6 times as fast as the POWER7 in single-threaded operations.

A POWER8 processor is a 12-chiplet design with variants consisting of either 4, 6, 8, 10 or 12 chiplets, where one chiplet consists of one core, 512 KB of SRAM L2 cache on a 64-byte wide bus (which is twice as wide as on its predecessor[1]), and 8 MB of L3 eDRAM cache per chiplet shareable among all chiplets.[14] Thus, a six-chiplet processor would have 48 MB of L3 eDRAM cache, while a 12-chiplet processor would have a total of 96 MB of L3 eDRAM cache. The chip can also utilize an up to 128 MB of off-chip eDRAM L4 cache using Centaur companion chips. The on-chip memory controllers can handle 1 TB of RAM and 230 GB/s sustained memory bandwidth. The on-board PCI Express controllers can handle 48 GB/s of I/O to other parts of the system. The cores are designed to handle clock rates between 2.5 and 5 GHz.[13]

The 6-core version is mounted in pairs on dual-chip modules (DCM) in IBM's Scale Out servers. In most configurations not all cores are active, resulting in a variety of configurations where the actual core count differs. The 12-core version has not been released in any system as of May 2014.

IBM's single-chip POWER8 module is called Turismo[5] and the dual-chip variant is called Murano.[22] PowerCore's modified version is called CP1.

Licensees

In 19 January 2014, the Suzhou PowerCore Technology Company announced that they will join the OpenPOWER Foundation and license the POWER8 core to design custom-made processors for use in big data and cloud computing applications.[23][24]

Variants

  • IBM Murano: a 12-core processor with two six-core chips. Scale-out processor is available in configurations with disabled cores.
  • IBM Turismo: a single-chip 12-core processor. Scale-up processor is commercially available for licensing and purchase in configurations with disabled cores.
  • PowerCore CP1 – a POWER8 variant with revised security features due to export restrictions between USA and China that will be manufactured in Global Foundries (formerly IBM's plant) factory in East Fishkill, New York. To be released in 2015.[25][26]

Systems

IBM
Scale Out servers, supporting one or two sockets each carrying a dual-chip module with two six-core POWER8 processors. They come in either 2U or 4U form factors, and one tower configuration. The "L" versions run only Linux, while the others run AIX, IBM i and Linux.[27][28][29]
  • Power Systems S812L – 1× POWER8 DCM (4, 6 or 8 cores), 2U
  • Power Systems S822 and S822L – 1× or 2× POWER8 DCM (6, 10, 12 or 20 cores), 2U
  • Power Systems S814 – 1× POWER8 DCM (6 or 8 cores), 4U or tower
  • Power Systems S824 and S824L – 1× or 2× POWER8 DCM (6, 8, 12, 16 or 24 cores), 4U
Enterprise servers, supporting nodes with four sockets, each carrying an 8-, 10 or 12-core modules, for a maximum of 16 sockets, 128 cores and 16 TB or RAM. These machines can run AIX, IBM i, or Linux.[30]
  • Power Systems E850 – 2×, 3× or 4× POWER8 DCM (8, 10 or 12 cores), 4U
  • Power Systems E870 – 1× or 2× 5U nodes, each with four sockets with 8- or 10-core POWER8 single-chip modules, for up to a total of 80 cores.
  • Power Systems E880 – 1x, 2x, 3x or 4x 5U nodes, each with four sockets with 8- or 12-core POWER8 single-chip modules for up to a total of 192 cores.
High performance computing:
  • Firestone – 2× POWER8 DCM, 2U. Manufactured by Wistron for IBM, with two Nvidia K40 GPUs and up to 1 TB commodity DDR3 RAM.[25][31][32]
TYAN
  • An ATX motherboard with one single-chip POWER8 socket called the SP010GM2NR.[5]
  • Palmetto GN70-BP010, OpenPower reference system. 2U server, with one four-core POWER8 SCM, four RAM sockets, based on a TYAN's motherboard.[5][33]
  • Habanero TN-71-BP012. 2U, with one eight-core POWER8 SCM, 32 RAM sockets[25][33][32]
Google
Google has shown a motherboard with two sockets, intended for internal use only.[34][35]
Inspur
Inspur has made a deal with IBM to develop server hardware based on POWER8 and related technologies.[36][37]
  • 4U server, two POWER8 sockets.[38]
Cirrascale
RM4950 – 4U, 4-core POWER8 SCM with four Nvidia Tesla K40 accelerators. Based on TYAN's motherboard.[25][39][31][32]
Zoom Netcom
RedPower C210 and C220 – 4U servers with two CP1 sockets and 64 RAM sockets.[25]
ChuangHe
OP-1X – 1U, single socket, 32 RAM slots.[25][40]
Rackspace
Barreleye – 1U, 2 socket, 32 RAM slots. Based on the Open Compute Project plattform for use in their OnMetal service.[41][32][42][40][43]

See also

References

  1. ^ a b c d You won't find this in your phone: A 4GHz 12-core Power8 for badass boxes
  2. ^ POWER8 Processor User’s Manual for the Single-Chip Module
  3. ^ a b IBM POWER8 - Announce / Availability Plans
  4. ^ Agam Shah (17 December 2014). "Non-IBM Power8 servers, chips to appear early next year". CIO. Retrieved 17 December 2014.
  5. ^ a b c d "Tyan Ships First Non-IBM Power8 Server". EnterpriseTech. Retrieved 17 December 2014.
  6. ^ "IBM's Watson could get even smarter with Power8 chip". idgconnect.com. Retrieved 17 December 2014.
  7. ^ Agam Shah (17 December 2014). "IBM's new Power8 doubles performance of Watson chip". PC World. Retrieved 17 December 2014.
  8. ^ "IBM Power8 Processor Detailed - Features 22nm Design With 12 Cores, 96 MB eDRAM L3 Cache and 4 GHz Clock Speed". WCCFtech. Retrieved 17 December 2014.
  9. ^ Altavilla, Dave (18 November 2013). "Nvidia Unveils Tesla K40 Accelerator And Strategic Partnership With IBM". forbes.com. Forbes. Retrieved 18 November 2013.
  10. ^ Todd Rosedahl (2014-12-20). "OCC Firmware Code is Now Open Source". openpowerfoundation.org. Retrieved 2014-12-27.
  11. ^ "open-power/docs: OCC Overview". github.com. 2014-12-09. Retrieved 2014-12-27.
  12. ^ "Semiconductor Engineering .:. The Good Kind Of Regulation". Retrieved 17 December 2014.
  13. ^ a b Frédéric Rémond. "ISSCC 2014 - IBM dévoile le Power8". Retrieved 17 December 2014.
  14. ^ a b Hurlimann, Dan (June 2014). "POWER8 Hardware" (PDF). ibm.com. IBM. Retrieved 2014-11-05.
  15. ^ "IBM Power System S814". Retrieved 17 December 2014.
  16. ^ "POWER8: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth". Retrieved 17 December 2014.
  17. ^ a b Jeff Stuecheli (2013-10-18). "An introduction to POWER8 processor" (PDF). IBM Corporation. pp. 15–17. Retrieved 2014-05-01.
  18. ^ "Memory Bandwidth Takes Center Stage at Hot Chips Conference". Altera.com. 2013-11-22. Retrieved 2014-05-01.
  19. ^ "Performance Optimization and Tuning Techniques for IBM Processors, including IBM POWER8" (PDF). IBM. July 2014. Retrieved February 8, 2015.
  20. ^ Wei Li (November 18, 2014). "IBM XL compiler hardware transactional memory built-in functions for IBM AIX on IBM POWER8 processor-based systems". IBM. Retrieved February 8, 2015.
  21. ^ Harold W. Cain, Maged M. Michael, Brad Frey, Cathy May, Derek Williams, and Hung Le. "Robust Architectural Support for Transactional Memory in the Power Architecture." In ISCA '13 Proceedings of the 40th Annual International Symposium on Computer Architecture, pp. 225-236, ACM, 2013. doi:10.1145/2485922.2485942
  22. ^ Power8 Iron To Take On Four-Socket Xeons
  23. ^ "IBM News room - 2014-01-19 Suzhou PowerCore Technology Co. Intends To Use IBM POWER Technology For Chip Design That Pushes Innovation In China - United States". 03.ibm.com. Retrieved 2014-01-22.
  24. ^ Chris Maxcer and Mel Beckman. "Suzhou PowerCore to Start Using IBM POWER Tech for New Chip Design in China". PowerITPro. Retrieved 2014-01-22.
  25. ^ a b c d e f OpenPower Collective Opens For System Business
  26. ^ Foundation Unveils Slew of OpenPOWER Firsts
  27. ^ IBM Announces POWER8 with OpenPOWER Partners
  28. ^ "IBM News room - 2014-04-23 IBM Tackles Big Data Challenges with Open Server Innovation Model - United States". Retrieved 17 December 2014.
  29. ^ Scale-out Hardware with POWER8 Technology
  30. ^ IBM Power Systems E870 and E880 Technical Overview and Introduction
  31. ^ a b IBM’s First OpenPOWER Server Targets HPC Workloads
  32. ^ a b c d OpenPOWER Foundation Technology Leaders Unveil Hardware Solutions To Deliver New Server Alternatives
  33. ^ a b TYAN OpenPOWER System
  34. ^ "Inside Google, Tyan Power8 Server Boards". EnterpriseTech. Retrieved 17 December 2014.
  35. ^ "Today I'm excited to show off a Google POWER8 server motherboard in the…". Retrieved 17 December 2014.
  36. ^ "IBM to help China's Inspur to design servers". Reuters. Retrieved 17 December 2014.
  37. ^ Alex Barinka (23 August 2014). "IBM Sets Aside Rivalry to Partner With China's Inspur". Bloomberg. Retrieved 17 December 2014.
  38. ^ 14 Views of the Open Power Summit
  39. ^ Cirrascale RM4950 / Multi-Device POWER8® Development Platform
  40. ^ a b OpenPower Group Puts Initial Hardware Products on Display
  41. ^ OpenPOWER: Opening The Stack, All The Way Down
  42. ^ Rackspace Building OpenPOWER-Based Open Compute Server
  43. ^ Life at the Intersection: OpenPOWER, Open Compute, and the Future of Cloud Software & Infrastructure
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