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NVLink

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This is an old revision of this page, as edited by 115.133.27.58 (talk) at 13:01, 4 May 2021 (https://www.nvidia.com/en-us/data-center/grace-cpu/ The fourth-generation NVIDIA NVLink delivers 900 gigabytes per second (GB/s) of bidirectional bandwidth between the NVIDIA Grace CPU and NVIDIA GPUs.). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

NVLink
ManufacturerNvidia
TypeMulti-GPU and CPU
PredecessorScalable Link Interface

NVLink is a wire-based serial multi-lane near-range communications link developed by Nvidia. Unlike PCI Express, a device can consist of multiple NVLinks, and devices use mesh networking to communicate instead of a central hub. The protocol was first announced in March 2014 and uses a proprietary high-speed signaling interconnect (NVHS).[1]

Principle

NVLink is a wire-based communications protocol for near-range semiconductor communications developed by Nvidia that can be used for data and control code transfers in processor systems between CPUs and GPUs and solely between GPUs. NVLink specifies a point-to-point connection with data rates of 20, 25 and 50 Gbit/s (v1.0/v2.0/v3.0 resp.) per differential pair. Eight differential pairs form a "sub-link" and two "sub-links", one for each direction, form a "link". The total data rate for a sub-link is 25 Gbit/s and the total data rate for a link is 50 Gbit/s. Each V100 GPU supports up to six links. Thus, each GPU is capable of supporting up to 300 Gbit/s in total bi-directional bandwidth.[2][3] NVLink products introduced to date focus on the high-performance application space. Announced May 14, 2020, NVLink 3.0 increases the data rate per differential pair from 25 Gbit/s to 50 Gbit/s while halving the number of pairs per NVLink from 8 to 4. With 12 links for an Ampere-based A100 GPU this brings the total bandwidth to 600 GB/sec.[4]

Performance

The following table shows a basic metrics comparison based upon standard specifications:

Interconnect Transfer
rate		 Line code Effective payload rate
per lane
per direction		 Max total
lane length
(PCIe: incl. 5" for PCBs)		 Realized in design
PCIe 1.x 2.5 GT/s 8b/10b ~0.25 GB/s 20" = ~51 cm
PCIe 2.x 5 GT/s 8b/10b ~0.5 GB/s 20" = ~51 cm
PCIe 3.x 8 GT/s 128b/130b ~1 GB/s 20" = ~51 cm[5] Pascal,
Volta,
Turing
PCIe 4.0 16 GT/s 128b/130b ~2 GB/s 8−12" = ~20−30 cm[5] Volta on Xavier
(8x, 4x, 1x),
Ampere,
Power 9
PCIe 5.0 32 GT/s[6] 128b/130b ~4 GB/s
PCIe 6.0 64 GT/s 128b/130b ~8 GB/s
NVLink 1.0 20 Gbit/s ~2.5 GB/s Pascal,
Power 8+
NVLink 2.0 25 Gbit/s ~3.125 GB/s Volta,
NVSwitch for Volta
Power 9
NVLink 3.0 50 Gbit/s ~6.25 GB/s Ampere,
NVSwitch for Ampere
NVLink 4.0 ?? Gbit/s ~?.?? GB/s Nvidia Grace Datacenter/Server CPU,
Next-Gen Nvidia GPU microarchitecture

The following table shows a comparison of relevant bus parameters for real world semiconductors that all offer NVLink as one of their options:

Semiconductor Board/bus
delivery variant		 Interconnect Transmission
technology
rate (per lane)		 Lanes per
sub-link
(out + in)		 Sub-link data rate
(per data direction)		 Sub-link
or unit
count		 Total data rate
(out + in)		 Total
lanes
(out + in)		 Total
data rate
(out + in)
Nvidia GP100 P100 SXM[7],
P100 PCI-E[8]		 PCIe 3.0 08 GT/s 16 + 16 Ⓑ 128 Gbit/s = 16 GByte/s 1 016 + 016 GByte/s[9] 32 Ⓒ 032 GByte/s
Nvidia GV100 V100 SXM2[10],
V100 PCI-E[11]		 PCIe 3.0 08 GT/s 16 + 16 Ⓑ 128 Gbit/s = 16 GByte/s 1 016 + 016 GByte/s 32 Ⓒ 032 GByte/s
Nvidia TU104 GeForce RTX 2080,
Quadro RTX 5000		 PCIe 3.0 08 GT/s 16 + 16 Ⓑ 128 Gbit/s = 16 GByte/s 1 016 + 016 GByte/s 32 Ⓒ 032 GByte/s
Nvidia TU102 GeForce RTX 2080 Ti,
Quadro RTX 6000/8000		 PCIe 3.0 08 GT/s 16 + 16 Ⓑ 128 Gbit/s = 16 GByte/s 1 016 + 016 GByte/s 32 Ⓒ 032 GByte/s
Nvidia Xavier[12] (generic) PCIe 4.0 Ⓓ
2 units: x8 (dual)
1 unit: x4 (dual)
3 units: x1[13][14]		 16 GT/s
08 + 08 Ⓑ
04 + 04 Ⓑ
1 + 010
128 Gbit/s = 16 GByte/s
64 Gbit/s = 08 GByte/s
16 Gbit/s = 02 GByte/s		 Ⓓ
2
1
3		 Ⓓ
032 + 032 GByte/s
008 + 008 GByte/s
006 + 006 GByte/s		 40 Ⓑ 80 GByte/s
IBM Power9[15] (generic) PCIe 4.0 16 GT/s 16 + 16 Ⓑ 256 Gbit/s = 32 GByte/s 3 096 + 096 GByte/s 96 192 GByte/s
Nvidia GA100[16][17]

Nvidia GA102[18]

Ampere A100 PCIe 4.0 016 GT/s 16 + 16 Ⓑ 256 Gbit/s = 32 GByte/s 1 032 + 032 GByte/s 32 Ⓒ 064 GByte/s
Nvidia GP100 P100 SXM,
(not available with P100 PCI-E)[19]		 NVLink 1.0 20 GT/s 08 + 08 Ⓐ 160 Gbit/s = 20 GByte/s 4 080 + 080 GByte/s 64 160 GByte/s
Nvidia Xavier (generic) NVLink 1.0[12] 20 GT/s[12] 08 + 08 Ⓐ 160 Gbit/s = 20 GByte/s[20]
IBM Power8+ (generic) NVLink 1.0 20 GT/s 08 + 08 Ⓐ 160 Gbit/s = 20 GByte/s 4 080 + 080 GByte/s 64 160 GByte/s
Nvidia GV100 V100 SXM2[21]
(not available with V100 PCI-E)		 NVLink 2.0 25 GT/s 08 + 08 Ⓐ 200 Gbit/s = 25 GByte/s 6[22] 150 + 150 GByte/s 96 300 GByte/s
IBM Power9[23] (generic) NVLink 2.0
(BlueLink ports)		 25 GT/s 08 + 08 Ⓐ 200 Gbit/s = 25 GByte/s 6 150 + 150 GByte/s 96 300 GByte/s
NVSwitch
for Volta[24]		 (generic)
(fully connected 18x18 switch)		 NVLink 2.0 25 GT/s 08 + 08 Ⓐ 200 Gbit/s = 25 GByte/s 2 * 8 + 2
= 18		 450 + 450 GByte/s 288 900 GByte/s
Nvidia TU104 GeForce RTX 2080,
Quadro RTX 5000[25]		 NVLink 2.0 25 GT/s 08 + 08 Ⓐ 200 Gbit/s = 25 GByte/s 1 025 + 025 GByte/s 16 050 GByte/s
Nvidia TU102 GeForce RTX 2080 Ti,
Quadro RTX 6000/8000[25]		 NVLink 2.0 25 GT/s 08 + 08 Ⓐ 200 Gbit/s = 25 GByte/s 2 050 + 050 GByte/s 32 100 GByte/s
Nvidia GA100[16][17] Ampere A100 NVLink 3.0 50 GT/s 04 + 04 Ⓐ 200 Gbit/s = 25 GByte/s 12[26] 300 + 300 GByte/s 96 600 GByte/s
Nvidia GA102[27] GeForce RTX 3090
Quadro RTX A6000		 NVLink 3.0 28,125 GT/s 04 + 04 Ⓐ 112,5 Gbit/s = 14,0625 GByte/s 4 56.25 + 56.25 GByte/s 16 112.5 GByte/s
NVSwitch
for Ampere[28]		 (generic)
(fully connected 18x18 switch)		 NVLink 3.0 50 GT/s 08 + 08 Ⓐ 400 Gbit/s = 50 GByte/s 2 * 8 + 2
= 18		 900 + 900 GByte/s 288 1800 GByte/s

Note: Data rate columns were rounded by being approximated by transmission rate, see real world performance paragraph

Ⓐ: sample value; NVLink sub-link bundling should be possible
Ⓑ: sample value; other fractions for the PCIe lane usage should be possible
Ⓒ: a single (no! 16) PCIe lane transfers data over a differential pair
Ⓓ: various limitations of finally possible combinations might apply due to chip pin muxing and board design
dual: interface unit can either be configured as a root hub or an end point
generic: bare semiconductor without any board design specific restrictions applied

Real world performance could be determined by applying different encapsulation taxes as well usage rate. Those come from various sources:

  • 128b/130b line code (see e.g. PCI Express data transmission for versions 3.0 and higher)
  • Link control characters
  • Transaction header
  • Buffering capabilities (depends on device)
  • DMA usage on computer side (depends on other software, usually negligible on benchmarks)

Those physical limitations usually reduce the data rate to between 90 and 95% of the transfer rate. NVLink benchmarks show an achievable transfer rate of about 35.3 Gbit/s (host to device) for a 40 Gbit/s (2 sub-lanes uplink) NVLink connection towards a P100 GPU in a system that is driven by a set of IBM Power8 CPUs.[29]

Usage with plug-In boards

For the various versions of plug-in boards (a yet small number of high-end gaming and professional graphics GPU boards with this feature exist) that expose extra connectors for joining them into a NVLink group, a similar number of slightly varying, relatively compact, PCB based interconnection plugs does exist. Typically only boards of the same type will mate together due to their physical and logical design. For some setups two identical plugs need to be applied for achieving the full data rate. As of now the typical plug is U-shaped with a fine grid edge connector on each of the end strokes of the shape facing away from the viewer. The width of the plug determines how far away the plug-in cards need to be seated to the main board of the hosting computer system - a distance for the placement of the card is commonly determined by the matching plug (known available plug widths are 3 to 5 slots and also depend on board type).[30][31] The interconnect is often referred as SLI (Scalable Link Interface) from 2004 for its structural design and appearance, even if the modern NVLink based design is of a quite different technical nature with different features in its basic levels compared to the former design. Reported real world devices are:[32]

  • Quadro GP100 (a pair of cards will make use of up to 2 bridges;[33] the setup realizes either 2 or 4 NVLink connections with up to 160 GB/s[34] - this might resemble NVLink 1.0 with 20 GT/s)
  • Quadro GV100 (a pair of cards will need up to 2 bridges and realize up to 200 GB/s[30] - this might resemble NVLink 2.0 with 25 GT/s and 4 links)
  • GeForce RTX 2080 based on TU104 (with single bridge "GeForce RTX NVLink-Bridge"[35])
  • GeForce RTX 2080 Ti based on TU102 (with single bridge "GeForce RTX NVLink-Bridge"[31])
  • Quadro RTX 5000[36] based on TU104[37] (with single bridge "NVLink" up to 50 GB/s[38] - this might resemble NVLink 2.0 with 25 GT/s and 1 link)
  • Quadro RTX 6000[36] based on TU102[37] (with single bridge "NVLink HB" up to 100 GB/s[38] - this might resemble NVLink 2.0 with 25 GT/s and 2 links)
  • Quadro RTX 8000[36] based on TU102[39] (with single bridge "NVLink HB" up to 100 GB/s[38] - this might resemble NVLink 2.0 with 25 GT/s and 2 links)

Service software and programming

For the Tesla, Quadro and Grid product lines, the NVML-API (Nvidia Management Library API) offers a set of functions for programmatically controlling some aspects of NVLink interconnects on Windows and Linux systems, such as component evaluation and versions along with status/error querying and performance monitoring.[40] Further, with the provision of the NCCL library (Nvidia Collective Communications Library) developers in the public space shall be enabled for realizing e.g. powerful implementations for artificial intelligence and similar computation hungry topics atop NVLink.[41] The page "3D Settings" » "Configure SLI, Surround, PhysX" in the Nvidia Control panel and the CUDA sample application "simpleP2P" use such APIs to realize their services in respect to their NVLink features. On the Linux platform, the command line application with sub-command "nvidia-smi nvlink" provides a similar set of advanced information and control.[32]

History

On 5 April 2016, Nvidia announced that NVLink would be implemented in the Pascal-microarchitecture-based GP100 GPU, as used in, for example, Nvidia Tesla P100 products.[42] With the introduction of the DGX-1 high performance computer base it was possible to have up to eight P100 modules in a single rack system connected to up to two host CPUs. The carrier board (...) allows for a dedicated board for routing the NVLink connections – each P100 requires 800 pins, 400 for PCIe + power, and another 400 for the NVLinks, adding up to nearly 1600 board traces for NVLinks alone (...).[43] Each CPU has direct connection to 4 units of P100 via PCIe and each P100 has one NVLink each to the 3 other P100s in the same CPU group plus one more NVLink to one P100 in the other CPU group. Each NVLink (link interface) offers a bidirectional 20 GB/sec up 20 GB/sec down, with 4 links per GP100 GPU, for an aggregate bandwidth of 80 GB/sec up and another 80 GB/sec down.[44] NVLink supports routing so that in the DGX-1 design for every P100 a total of 4 of the other 7 P100s are directly reachable and the remaining 3 are reachable with only one hop. According to depictions in Nvidia's blog-based publications, from 2014 NVLink allows bundling of individual links for increased point to point performance so that for example a design with two P100s and all links established between the two units would allow the full NVLink bandwidth of 80 GB/s between them.[45]

At GTC2017, Nvidia presented its Volta generation of GPUs and indicated the integration of a revised version 2.0 of NVLink that would allow total I/O data rates of 300 GB/s for a single chip for this design, and further announced the option for pre-orders with a delivery promise for Q3/2017 of the DGX-1 and DGX-Station high performance computers that will be equipped with GPU modules of type V100 and have NVLink 2.0 realized in either a networked (two groups of four V100 modules with inter-group connectivity) or a fully interconnected fashion of one group of four V100 modules.

In 2017-2018, IBM and Nvidia delivered the Summit and Sierra supercomputers for the US Department of Energy[46] which combine IBM's POWER9 family of CPUs and Nvidia's Volta architecture, using NVLink 2.0 for the CPU-GPU and GPU-GPU interconnects and InfiniBand EDR for the system interconnects.[47]

In 2020 Nvidia announced that they will no longer be adding new SLI driver profiles on RTX 2000 series and older from January 1st, 2021.[48]

See also

References

  1. ^ Nvidia NVLINK 2.0 arrives in IBM servers next year by Jon Worrel on fudzilla.com on August 24, 2016
  2. ^ "NVIDIA DGX-1 With Tesla V100 System Architecture" (PDF).
  3. ^ "What Is NVLink?". Nvidia. 2014-11-14.
  4. ^ Ryan Smith (May 14, 2020). "NVIDIA Ampere Unleashed: NVIDIA Announces New GPU Architecture, A100 GPU, and Accelerator". AnandTech.
  5. ^ a b "PCIe - PCI Express (1.1 / 2.0 / 3.0 / 4.0 / 5.0)". www.elektronik-kompendium.de.
  6. ^ January 2019, Paul Alcorn 17. "PCIe 5.0 Is Ready For Prime Time". Tom's Hardware.{{cite web}}: CS1 maint: numeric names: authors list (link)
  7. ^ online, heise. "NVIDIA Tesla P100 [SXM2], 16GB HBM2 (NVTP100-SXM) | heise online Preisvergleich / Deutschland". geizhals.de.
  8. ^ online, heise. "PNY Tesla P100 [PCIe], 16GB HBM2 (TCSP100M-16GB-PB/NVTP100-16) ab € 4990,00 (2020) | heise online Preisvergleich / Deutschland". geizhals.de.
  9. ^ NVLink Takes GPU Acceleration To The Next Level by Timothy Prickett Morgan at nextplatform.com on May 4, 2016
  10. ^ "NVIDIA Tesla V100 SXM2 16 GB Specs". TechPowerUp.
  11. ^ online, heise. "PNY Quadro GV100, 32GB HBM2, 4x DP (VCQGV100-PB) ab € 10199,00 (2020) | heise online Preisvergleich / Deutschland". geizhals.de.
  12. ^ a b c Tegra Xavier - Nvidia at wikichip.org
  13. ^ JETSON AGX XAVIER PLATFORM ADAPTATION AND BRING-UP GUIDE "Tegra194 PCIe Controller Features" on page 14; stored at arrow.com
  14. ^ How to enable PCIe x2 slot with Xavier? on devtalk.nvidia.com
  15. ^ POWER9 Webinar presentation by IBM for Power Systems VUG by Jeff Stuecheli on January 26, 2017
  16. ^ a b Morgan, Timothy Prickett (May 14, 2020). "Nvidia Unifies AI Compute With "Ampere" GPU". The Next Platform.
  17. ^ a b "Data sheet" (PDF). www.nvidia.com. Retrieved 2020-09-15.
  18. ^ https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/ampere/pdf/NVIDIA-ampere-GA102-GPU-Architecture-Whitepaper-V1.pdf
  19. ^ All aboard the PCIe bus for Nvidia's Tesla P100 supercomputer grunt by Chris Williams at theregister.co.uk on June 20, 2016
  20. ^ Hicok, Gary (November 13, 2018). "NVIDIA Xavier Achieves Milestone for Safe Self-Driving | NVIDIA Blog". The Official NVIDIA Blog.
  21. ^ online, heise. "Nvidia Tesla V100: PCIe-Steckkarte mit Volta-Grafikchip und 16 GByte Speicher angekündigt". heise online.
  22. ^ GV100 Blockdiagramm in "GTC17: NVIDIA präsentiert die nächste GPU-Architektur Volta - Tesla V100 mit 5.120 Shadereinheiten und 16 GB HBM2" by Andreas Schilling on hardwareluxx.de on May 10, 2017
  23. ^ NVIDIA Volta GV100 GPU Chip For Summit Supercomputer Twice as Fast as Pascal P100 – Speculated To Hit 9.5 TFLOPs FP64 Compute by Hassan Mujtaba at wccftech.com on December 20, 2016
  24. ^ "Technical overview" (PDF). images.nvidia.com. Retrieved 2020-09-15.
  25. ^ a b Angelini, Chris (14 September 2018). "Nvidia's Turing Architecture Explored: Inside the GeForce RTX 2080". Tom's Hardware. p. 7. Retrieved 28 February 2019. TU102 and TU104 are Nvidia's first desktop GPUs rocking the NVLink interconnect rather than a Multiple Input/Output (MIO) interface for SLI support. The former makes two x8 links available, while the latter is limited to one. Each link facilitates up to 50 GB/s of bidirectional bandwidth. So, GeForce RTX 2080 Ti is capable of up to 100 GB/s between cards and RTX 2080 can do half of that.
  26. ^ https://www.hardwareluxx.de/index.php/news/hardware/grafikkarten/53450-a100-pcie-nvidia-ga100-gpu-kommt-auch-als-pci-express-variante.html
  27. ^ https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/ampere/pdf/NVIDIA-ampere-GA102-GPU-Architecture-Whitepaper-V1.pdf
  28. ^ "NVLINK AND NVSWITCH". www.nvidia.com. Retrieved 2021-02-07.
  29. ^ Comparing NVLink vs PCI-E with NVIDIA Tesla P100 GPUs on OpenPOWER Servers by Eliot Eshelman on microway.com on January 26, 2017
  30. ^ a b "NVIDIA Quadro NVLink Grafikprozessor-Zusammenschaltung in Hochgeschwindigkeit". NVIDIA.
  31. ^ a b "Grafik neu erfunden: NVIDIA GeForce RTX 2080 Ti-Grafikkarte". NVIDIA.
  32. ^ a b "NVLink on NVIDIA GeForce RTX 2080 & 2080 Ti in Windows 10". Puget Systems.
  33. ^ [1][dead link]
  34. ^ Schilling, Andreas. "NVIDIA präsentiert Quadro GP100 mit GP100-GPU und 16 GB HBM2". Hardwareluxx.
  35. ^ "NVIDIA GeForce RTX 2080 Founders Edition Graphics Card". NVIDIA.
  36. ^ a b c "NVIDIA Quadro Graphics Cards for Professional Design Workstations". NVIDIA.
  37. ^ a b "NVIDIA Quadro RTX 6000 und RTX 5000 Ready für Pre-Order". October 1, 2018.
  38. ^ a b c "NVLink | pny.com". www.pny.com.
  39. ^ "NVIDIA Quadro RTX 8000 Specs". TechPowerUp.
  40. ^ "NvLink Methods". docs.nvidia.com.
  41. ^ "NVIDIA Collective Communications Library (NCCL)". NVIDIA Developer. May 10, 2017.
  42. ^ "Inside Pascal: NVIDIA's Newest Computing Platform". 2016-04-05.
  43. ^ Anandtech.com
  44. ^ NVIDIA Unveils the DGX-1 HPC Server: 8 Teslas, 3U, Q2 2016 by anandtech.com on April, 2016
  45. ^ How NVLink Will Enable Faster, Easier Multi-GPU Computing by Mark Harris on November 14, 2014
  46. ^ "Whitepaper: Summit and Sierra Supercomputers" (PDF). 2014-11-01.
  47. ^ "Nvidia Volta, IBM POWER9 Land Contracts For New US Government Supercomputers". AnandTech. 2014-11-17.
  48. ^ "RIP: Nvidia slams the final nail in SLI's coffin, no new profiles after 2020". PC_World. 2020-09-18.
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