PCI-X
| PCI Local Bus | |
 A PCI-X Gigabit Ethernet expansion card. |
|
| Year created | 1998 |
|---|---|
| Created by | IBM, HP, and Compaq |
| Superseded by | PCI Express (2004) |
| Width in bits | 64 |
| Number of devices | 1 per slot |
| Capacity | 1064 MB/s |
| Style | Parallel |
| Hotplugging interface | yes |
PCI-X is a computer bus and expansion card standard that enhances the 32-bit PCI Local Bus for higher bandwidth demanded by servers. It is a double-wide version of PCI, running at up to four times the clock speed, but is otherwise similar in electrical implementation and uses the same protocol.[1] It has itself been replaced in modern designs by the similar-sounding PCI Express, which features a very different logical design, most notably being a "narrow but fast" serial connection instead of a "wide but slow" parallel connection.
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[edit] Background
PCI-X was developed jointly by IBM, HP, and Compaq and submitted for approval in 1998. It was an effort to codify proprietary server extensions to the PCI local bus to increase performance of high bandwidth devices such as Gigabit Ethernet, Fibre Channel and Ultra3 SCSI cards and allow processors to be interconnected in clusters.
PCI-X was needed as some devices, most notably Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and cluster interconnects, could by themselves saturate the PCI bus' 133 MB/s bandwidth. Ports using a bus speed doubled to 66 MHz and a bus width doubled to 64 bits (with the pin count increased to 184 from 124), in combination or not, have been implemented. These extensions were loosely supported as optional parts of the PCI 2.x standards, but device compatibility beyond the basic 133 MB/s continued to be difficult.
Developers eventually used the combined 64-bit and 66-MHz extension as a foundation, and anticipating future needs, established 66-MHz and 133-MHz variants with a maximum bandwidth of 532 MB/s and 1064 MB/s respectively. The joint result was submitted as PCI-X to the PCI Special Interest Group (Special Interest Group of the Association for Computing Machinery). Subsequent approval made it an open standard adoptable by all computer developers. The PCI SIG controls technical support, training and compliance testing for PCI-X. IBM, Intel, Microelectronics and Mylex were to develop supporting chipsets. 3Com and Adaptec were to develop compatible peripherals. To accelerate PCI-X adoption by the industry, Compaq offered PCI-X development tools at their web site. All major chip makers generally now have or have had some variant of PCI-X in their product lines.
[edit] Technical description
PCI-X revised the conventional PCI standard by doubling the maximum clock speed (from 66 MHz to 133 MHz)[1] and hence the amount of data exchanged between the computer processor and peripherals. Conventional PCI supports up to 64 bits at 66 MHz (though anything above 32 bits at 33 MHz is only seen in high-end systems) and additional bus standards move 32 bits at 66 MHz or 64 bits at 33 MHz. The theoretical maximum amount of data exchanged between the processor and peripherals with PCI-X is 1.06 GB/s, compared to 133 MB/s with standard PCI. PCI-X also improves the fault tolerance of PCI allowing, for example, faulty cards to be reinitialized or taken offline.
PCI-X is generally backward-compatible with most cards based on the PCI 2.x[1] or later standard, meaning that a PCI card can be installed in a PCI-X slot, provided it has the correct voltage keying for the slot and (if inserting into a 32-bit slot) nothing obstructs the overhanging part of the edge connector. Originally the PCI bus was a 5-volt bus. Later, in PCI Revision 2.x, the PCI bus was a dual-voltage interconnect. In 3.0 this was changed to 3.3 volts only. The PCI-X bus is not compatible with the older 5-volt cards but newer 3.3-volt PCI cards will work in a PCI-X slot.[1] Apart from this, PCI and PCI-X cards can generally be intermixed on a PCI-X bus, but the speed will be limited to the speed of the slowest card. For example, a PCI 2.3 device running at 32 bits and 66 MHz on a PCI-X 133-MHz bus will limit the total throughput of the bus to 266 MB/s. To get around this limitation and the voltage compatibility issue, many motherboards have separate PCI-X channels that can be dedicated to different PCI hardware families if needed, allowing for better backward compatibility while maintaining higher total system bandwidth.
[edit] Versions
All PCI-X cards or slots have a 64-bit implementation and vary as follows:
- Cards
- Slots
- 66 MHz (can be found on older servers)
- 133 MHz (most common on modern servers)
- 266 MHz (rare, being replaced by PCI-e)
- 533 MHz (rare, being replaced by PCI-e)
[edit] PCI-X 2.0
In 2003, the PCI SIG ratified PCI-X 2.0. It adds 266-MHz and 533-MHz variants, yielding roughly 2.15 GB/s and 4.3 GB/s throughput, respectively. PCI-X 2.0 makes additional protocol revisions that are designed to help system reliability and add Error-correcting codes to the bus to avoid resends.[1] To deal with one of the most common complaints of the PCI-X form factor, the 184-pin connector, 16-bit ports were developed to allow PCI-X to be used in devices with tight space constraints. Similar to PCI-Express, PtP functions were added to allow for devices on the bus to talk to each other without burdening the CPU or bus controller.
Despite the various theoretical advantages of PCI-X 2.0 and its backward compatibility with PCI-X and PCI devices, it has not been implemented on a large scale (as of 2008). This lack of implementation is primarily because hardware vendors have chosen to integrate PCI Express instead.
[edit] Confusion with PCI-Express
PCI-X is often confused with PCI Express, commonly abbreviated as PCI-E or PCIe. The main source of this confusion is the fact that "PCI-X" sounds similar to "PCI Express". Visually there is no such similarity. While they are both high-speed computer buses for internal peripherals, they differ in many ways. The first is that PCI-X is a parallel interface that is directly backward compatible with all but the oldest (5-volt) standard PCI devices. PCIe is a serial bus with a different physical interface that was designed to supersede both PCI and PCI-X.
PCI-X and standard PCI buses may run on a PCIe bridge, similar to the way ISA buses ran on standard PCI buses in some computers. PCIe also matches PCI-X and even PCI-X 2.0 in maximum bandwidth. PCIe 1.0 x1 offers 250 MB/s in each direction, and up to 32 lanes (x32) is currently supported, giving a maximum of 8 GB/s in each direction.
PCI-X has a number of technological and economical disadvantages from PCI-Express. The 64-bit parallel interface requires inherently difficult trace routing, because as with all parallel interfaces, the signals from the bus must arrive simultaneously or within a very short window, and noise from adjacent slots may cause interference. The serial interface of PCIe suffers fewer such problems and therefore requires less complex and less expensive designs. PCI-X buses, like standard PCI, are half-duplex bidirectional whereas PCIe buses are full-duplex bidirectional. PCI-X buses run only as fast as the slowest device whereas PCIe devices are able to independently negotiate the bus speed. Also, PCI-X slots are longer than PCIe 1x through PCIe 16x, which makes it impossible to make short cards for PCI-X. PCI-X slots thus take quite a bit of space on motherboards, which can be a problem for ATX and smaller form factors.
[edit] See also
[edit] References
- ^ a b c d e f g h i "PCI-SIG — FAQ — PCI-X 2.0". http://www.pcisig.com/news_room/faqs/faq_20/. Retrieved 2008-02-17.
- ^ "PCI-X vs. PCI-Express". http://www.it-enquirer.com/main/ite/more/pci_xpci_express/. Retrieved 2008-02-17.[dead link]
