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10 nm process

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For the length in general and comparison, see 10 nanometres.
Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.

Background

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm. Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, claimed in 2008 that Intel saw a 'clear way' towards the 10 nm node.[1][2] At the 11 nm node, Intel expected (in 2006) to be using a half-pitch of around 21 nm, in 2015,[3] Nvidia's chief scientist, William Dally, claimed (in 2009) that they would also reach 11 nm semiconductors in 2015, a transition he claimed would be facilitated principally through new electronic design automation tools.[4]

As of 2014, "10 nm" node was projected to use a metal pitch of 40–50 nm.[5]

This 10 nm design rule is considered likely to be realized by multiple patterning,[6][7][8] given the difficulty of implementing EUV lithography.

Potential technologies

While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Scientists have estimated that transistors at these dimensions are significantly affected by quantum tunnelling.[9] As a result, non-silicon extensions of CMOS, using III-V materials or carbon nanotube/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics.

The extensive use of ultra-low-κ dielectrics (such as spin-on polymers or other porous materials) means that conventional photolithography, etch, or even chemical-mechanical polishing processes are unlikely to be used, because these materials contain a high density of voids and gaps. At the ~10 nm scale, quantum tunneling (especially through gaps) becomes a significant phenomenon.[10] Controlling gaps on these scales by means of electromigration can produce interesting electrical properties.[11]

Quantum tunneling may be advantageous if its effect on device behavior can be understood, and exploited, in the design. Future transistors may have insulating channels. An electron wave function decays exponentially in a "classically forbidden" region at a rate that can be controlled by the gate voltage. Interference effects are also possible;[12] Alternate option is in heavier mass semiconducting channels.[13] Photoemission electron microscopy (PEEM) data has been used to show that low energy electrons ~1.35 eV could travel as far as ~15 nm in SiO2, despite an average measured attenuation length of 1.18 nm.[14]

Technology demos and pre-production.

In 2012, IBM produced a sub-10 nm carbon nanotube transistor that outperformed silicon on speed and power.[15] "The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies," according to the abstract of the paper in Nano Letters.[16]

In April 2015, TSMC announced that 10 nm production would begin at the end of 2016.[17]

On 23 May 2015, Samsung Electronics showed off a 300 mm wafer of 10 nm FinFET chips.[18]

In c. August 2016, Intel began trial production at 10 nm.[19]

On 17 October 2016, Samsung Electronics announced mass production at 10 nm.[20]

On 29 March 2017, Samsung started preorders for their Samsung Galaxy S8 which uses Samsung's version of a "10 nm" processor.[21]

Shipping devices

As of mid-2016, semiconductor business Intel, and foundries at TSMC, and Samsung were all expected to ship or begin volume production of 10 nm devices in the first quarter of 2017, with foundry customers for 2017 including Qualcomm (Snapdragon 835) at Samsung, and Apple Inc. and MediaTek at TSMC.[22]

On 21 April 2017, Samsung started shipping their Samsung Galaxy S8 smartphone which uses the company's version of the 10 nm processor.[23]

On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC produced Apple A10X chips using the 10 nm FinFET process.[24]

On September 12, 2017 Apple announced Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC, using a 10 nm FinFET process and containing 4.3 billion transistors on a die 87.66 square millimetres.

10 nm process nodes

ITRS Logic Device

Ground Rules

Intel

(proposed)

Samsung TSMC
Process name 11/10nm 10nm 10nm 10nm
Transistor Fin Pitch (nm) 36 34 47 N/A
Transistor Fin Height 42 53 49 N/A
Transistor Gate Pitch (nm) 48 54 68 66
Interconnect pitch (nm) 36 36 51 44

Lower numbers are better. Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm Transistor Gate Pitch and 48 nm Interconnect Pitch. TSMC reported their 10 nm process as having a 64 nm Transistor Gate Pitch and 42 nm Interconnect Pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin pitch and fin height of Samsung's 10nm process were updated by MSSCORPS CO at SEMICON Taiwan 2017.[25][26][27][28][29]

However, TSMC's 10 nm process is reportedly denser than Intel's 14 nm process or Samsung's 10 nm process, thus giving TSMC a technological lead in terms of density.[30][31][32]

References

  1. ^ Damon Poeter. "Intel's Gelsinger Sees Clear Path To 10nm Chips". Archived from the original on 2009-06-22. Retrieved 2009-06-20. {{cite web}}: Unknown parameter |deadurl= ignored (|url-status= suggested) (help)
  2. ^ "MIT: Optical lithography good to 12 nanometers". Archived from the original on 2009-06-22. Retrieved 2009-06-20. {{cite web}}: Unknown parameter |deadurl= ignored (|url-status= suggested) (help)
  3. ^ Borodovsky, Y. (2006). "Marching to the beat of Moore's Law". Proc. SPIE. 6153. doi:10.1117/12.655176.
  4. ^ "Nvidia Chief Scientist: 11nm Graphics Chips with 5000 Stream Processors Due in 2015". XBit Labs. July 30, 2009. Archived from the original on September 3, 2009. Retrieved 2009-08-27. {{cite news}}: Unknown parameter |deadurl= ignored (|url-status= suggested) (help)
  5. ^ Who will lead at 10nm?
  6. ^ SEMICON West - Lithography Challenges and Solutions
  7. ^ J. Word et al., Proc. SPIE 6925 (2008).[full citation needed][failed verification]
  8. ^ Intel extending ArF lithography Archived July 14, 2011, at the Wayback Machine
  9. ^ "Intel scientists find wall for Moore's Law". ZDNet. December 1, 2003.
  10. ^ Naitoh, Y.; et al. (2007). "New Nonvolatile Memory Effect Showing Reproducible Large Resistance Ratio Employing Nano-gap Gold Junction". MRS Symposium Proceedings. 997: 0997–I04–08. doi:10.1557/PROC-0997-I04-08.
  11. ^ Kayashima, S.; et al. (2007). "Control of Tunnel Resistance of Nanogaps by Field-Emission-Induced Electromigration". Jap. J. Appl. Phys. 46 (36–40): L907–909. doi:10.1143/JJAP.46.L907.
  12. ^ Ahmed, Khaled; Schuegraf, Klaus (November 2011). "Transistor Wars: Rival architectures face off in a bid to keep Moore's Law alive". IEEE Spectrum: 50.
  13. ^ Mehrotra, S.; et al. (2013). "Engineering Nanowire n-MOSFETs at Lg < 8 nm". Preprint. arXiv:1303.5458.
  14. ^ Ballarotto, V. W.; et al. (2002). "Photoelectron emission microscopy of ultrathin oxide covered devices". JVST B. 20 (6): 2514–2518. doi:10.1116/1.1525007.
  15. ^ "IBM: Tiny carbon nanotube transistor outshines silicon". Cnet.com. January 30, 2012.
  16. ^ Franklin, Aaron D.; et al. (2012). "Sub-10 nm Carbon Nanotube Transistor". Nano Letters. 12 (2): 758–762. doi:10.1021/nl203701g.
  17. ^ "TSMC Launching 10 nm FinFET Process In 2016, 7nm In 2017". 19 April 2015. Retrieved 25 May 2015.
  18. ^ "Samsung vows to start 10nm chip production in 2016". 23 May 2015. Retrieved 16 July 2015.
  19. ^ Pirzada, Usman (Aug 2016), "Intel Starts Up 10nm Factory – Trial Production Will Begin This Quarter, 10nm Canonnonlake Processors On Track For 2H 2017", wccftech.com
  20. ^ [1]
  21. ^ http://www.samsung.com/uk/smartphones/galaxy-s8/performance/
  22. ^ Manners, David, "10nm Lines Up For Q1.", www.electronicsweekly.com
  23. ^ http://www.samsung.com/us/explore/galaxy-s8/buy/
  24. ^ techinsights.com. "10nm Rollout Marching Right Along". www.techinsights.com. Retrieved 2017-06-30.
  25. ^ "Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals".
  26. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF).
  27. ^ "14nm 16nm 10nm and 7nm - What we know now".
  28. ^ "Qualcomm Snapdragon 835 First to 10 nm".
  29. ^ "10 nm lithography process".
  30. ^ "Samsung's 14 nm LPE FinFET transistors".
  31. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF).
  32. ^ "Intel's 22nm Tri-Gate Transistors".
Preceded by
14 nm 		CMOS manufacturing processes Succeeded by
7 nm
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