|Samsung and announced in January 2011.|
|Type||synchronous dynamic random-access memory|
|Release date||September 2012|
In computing, DDR4 SDRAM, an abbreviation for double data rate (fourth generation) synchronous dynamic random-access memory, is a type of dynamic random-access memory (DRAM) with a high bandwidth interface expected to be released to the market sometime in 2013. It is one of several variants of DRAM, some of which have been in use since the early 1970s and is not compatible with any earlier type of random access memory (RAM) due to different signaling voltages, physical interface and other factors.
Its primary benefits compared to DDR3 include a higher range of clock frequencies and data transfer rates (2133–4266 MT/s compared to DDR3's 800 and higher) and lower voltage (1.05–1.2 V for DDR4, compared to 1.2–1.65 V for DDR3) with current remaining the same. DDR4 also anticipates a change in topology. It discards the multiple DIMMs per channel approach in favor of a point-to-point topology where each channel in the memory controller is connected to a single DIMM. Switched memory banks are also an anticipated option for servers.
Development and market history
Standards body JEDEC began working on a successor to DDR3 around 2005, about 2 years before the launch of DDR3 in 2007. The high-level architecture of DDR4 was planned for completion in 2008.
Some advance information was published in 2007, and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum (IDF). DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.
Subsequently, further details were revealed at MemCon 2010, Tokyo (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4"  with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably or definitely delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.
DDR4 is expected to represent 5% of the DRAM market in 2013, and to reach mass market adoption and 50% market penetration around 2015; the latter is comparable with the approximately 5 years taken for DDR3 to achieve mass market transition over DDR2. In part, this is because changes required to other components would impact all other parts of computer systems, which would need to be updated to work with DDR4.
In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since in 2009, DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung announced the completion and release for testing of a 2 GB DDR4 DRAM module based on a process between 30 and 39 nm. It has a maximum data transfer rate of 2133 MT/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR memory) and draws 40% less power than an equivalent DDR3 module.
Three months later in April 2011, Hynix announced the production of 2 GB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified), adding that it anticipated commencing high volume production in the second half of 2012. Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.
In July 2012, Samsung Electronics Co., Ltd., announced that it has begun sampling the industry's first 16 GB registered dual inline memory modules (RDIMMs) using DDR4 SDRAM for enterprise server systems.
In September 2012 JEDEC released the final specification of DDR4.
Market perception and prospects
In April 2013, a news writer at International Data Group (IDG) – an American technology research business originally part of IDC – produced an analysis of their perceptions related to DDR4 SDRAM. The conclusions were that the increasing popularity of mobile computing and other devices using slower but low powered memory, the slowing of growth in the traditional desktop computing sector, and the consolidation of the memory manufacturing marketplace, meant that margins on RAM were tight. As a result the looked-for premium pricing used for initial profitability when introducing new technology to the marketplace, was harder to achieve, and capacity had shifted to other sectors; SDRAM manufacturers and chipset creators were to an extent caught in a "chicken and egg" situation where, according to iSupply, "Nobody wants to pay a premium for DDR4 products, and manufacturers don't want to make the memory if they are not going to get a premium". A switch in market sentiment towards desktop computing and release of chipsets having DDR4 support by Intel and AMD could therefore potentially lead to "aggressive" growth.
The new chips will use a 1.2 V supply:16 with a 2.5 V auxiliary supply for wordline boost called VPP,:16, versus the standard 1.5 V of DDR3 chips, with lower voltage variants at 1.05 V appearing in 2013. DDR4 is expected to be introduced at transfer rates of 2133 MT/s,:18 estimated to rise to a potential 4266 MT/s by 2013. The minimum transfer rate of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 MT/s, left little commercial benefit to specifying DDR4 below this speed. Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3.
Internal banks are increased to 16 (4 bank select bits), with up to 8 ranks per DIMM.:16
Protocol changes include::20
- Parity on the command/address bus
- Data bus inversion (like GDDR4)
- CRC on the data bus
- Independent programming of individual DRAMs on a DIMM, to allow better control of on-die termination.
Increased memory density is anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes. The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC, with provision for up to 8 stacked dies.:12 X-bit Labs predicted that "as a result DDR4 memory chips with very high density will become relatively inexpensive". Prefetch remains at 8n:16 with bank groups, including the use of two or four selectable bank groups.
DDR4 also anticipates a change in topology.[disputed ] It discards the multi-drop bus approach used in previous generations in favor of point-to-point where each channel in the memory controller is connected to a single module. This mirrors the trend also seen in the earlier transition from PCI to PCI Express, where parallelism was moved from the interface to the controller, and is likely to simplify timing in modern high-speed data buses. Switched memory banks are also an anticipated option for servers.
In 2008, concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedance, and increasing need for sense amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that as a result, the amount of die used for the memory array itself has declined over time from 70–78% with SDRAM and DDR1, to 47% for DDR2, to 38% for DDR3 and potentially to less than 30% for DDR4.
Although it still operates in fundamentally the same way, DDR4 makes one major change to the command formats used by previous SDRAM generations. A new command signal /ACT is low to indicate the activate (open row) command.
The activate command requires more address bits than any other (18 row address bits in an 8 Gb part), so the standard /RAS, /CAS and /WE signals are shared with high-order address bits that are not used when /ACT is high. The combination of /RAS=L, /CAS=H and /WE=H that previously encoded an activate command is unused.
As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs all banks for the precharge command. It also selects two variants of the ZQ calibration command.
In addition, A12 is used to request burst chop: truncation of an 8-transfer burst after 4 transfers. Although the bank is still busy and unavailable for other commands until 8 transfer times have elapsed, a different bank can be accessed.
Also, the number of bank addresses has been increased greatly. There are 4 bank select bits to select up to 16 banks within each DRAM: 2 bank address bits (BA0, BA1), and 2 bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group.
In addition, there are 3 chip select signals (C0, C1, C2), allowing up to 8 stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to 7 (128 possible banks).
|H||— x —||Deselect (No operation)|
|L||bank||L||Row address||Active (activate): open a row|
|L||x||H||x||H||H||H||— x —||No operation|
|L||bank||H||x||H||L||H||x||BC||x||AP||Column||Read (BC=burst chop)|
|L||x||H||x||L||H||H||— x —||(Unassigned, reserved)|
|L||x||H||x||L||H||L||x||H||x||Precharge all banks|
|L||bank||H||x||L||H||L||x||L||x||Precharge one bank|
|L||x||H||x||L||L||H||— x —||Refresh|
|L||register||H||0||L||L||L||0||data||Mode register set (MR0–MR6)|
Note: x bits are "don't care", but must be at a valid voltage level, either 0 or 1.
Standard transfer rates are 1600, 1866, 2133 and 2400 MT/s. (12/15, 14/15, 16/15 and 18/15 GHz clock speeds, double data rate.) 2666 and 3200 MT/s (20/15 and 24/15 GHz clock speeds) are provided for, but the specifications are not yet complete.
- VrefDQ calibration (DDR4 "requires that VrefDQ calibration be performed by the controller");
- New addressing schemes ("bank grouping", ACT_n to replace RAS#, CAS#, and WE# commands, PAR and Alert_n for error checking and DBI_n for data bus inversion);
- New power saving features (Low Power Auto Self Refresh, Temperature Controlled Refresh, Fine Granularity Refresh, Data Bus Inversion, and CMD/ADDT latency).
Circuit board design:
- New power supplies (VDD/VDDQ at 1.2V and wordline boost, known as VPP, at 2.5V);
- VrefDQ must be supplied internal to the DRAM while VrefCA is supplied externally from the board;
- DQ pins terminate high using pseudo-open-drain I/O (this differs from the CA pins in DDR3 which are center-tapped to VTT).
DDR4 memory comes in a 284-pin DIMM modules, similar to a 240-pin DDR-2/DDR-3 DIMM.:11 The pins are spaced more closely (0.85 mm instead of 1.0) to fit more within the standard 5-inch (133.35 mm) DIMM width, the height is increased slightly (31.25 mm/1.23 in instead of 30.35 mm/1.2 in) to make signal routing easier, and the thickness is increased (to 1.2 mm from 1.0) to accommodate more signal layers. 1⁄4
DDR4 SO-DIMMs have 256 pins (rather than 204), spaced closer (0.5 mm rather than 0.6), and are 1.0 mm wider (68.6 mm rather than 67.6), but retain the same 30 mm height.:11
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- Synchronous dynamic random access memory – main article for DDR memory types
- List of device bandwidths
- SDRAM latency