Resistive random-access memory

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Resistive random-access memory (RRAM or ReRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material known as memristor. This technology bears some similarities to CBRAM and phase-change memory.

RRAM is currently under development by a number of companies, some of which have filed patent applications claiming various implementations of this technology.[1][2][3][4][5][6][7] However, as of 2014 no commercial RRAM product is available for purchase.

History[edit]

In February 2012 Rambus bought a RRAM company called Unity Semiconductor for $35 million.[8] Panasonic launched a RRAM evaluation kit in May 2012, based on a tantalum oxide 1T1R (1 transistor - 1 resistor) memory cell architecture.[9]

In 2013, Crossbar introduced an RRAM prototype as a chip about the size of a postage stamp that could store 1 TB of data. In August 2013, the company claimed that large-scale production of their RRAM chips was scheduled for 2015.[10]

Different forms of RRAM have been disclosed, based on different dielectric materials, spanning from perovskites to transition metal oxides to chalcogenides. Silicon dioxide was shown to exhibit resistive switching as early as 1967,[11] and has recently been revisited.[12][13]

Leon Chua argued that all two-terminal non-volatile memory devices including RRAM should be considered memristors.[14] Stan Williams of HP Labs also argued that RRAM was a memristor.[15] However, others challenged this terminology by and the applicability of memristor theory to any physically realizable device is open to question.[16][17] Whether redox-based resistively switching elements (RRAM) are covered by the current memristor theory is disputed.[18]

In 2014 researchers announced a device that used a porous silicon oxide dielectric with no edge structure. In 2010 conductive filament pathways were discovered, leading to the later advance. It can be manufactured at room temperature and has a sub-2V forming voltage, higher on-off ratio, lower power consumption, nine-bit capacity per cell, higher switching speeds and improved endurance.[19]

Mechanism[edit]

The basic idea is that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage. The conduction path can arise from different mechanisms, including defects or metal migration. Once the filament is formed, it may be RESET(broken, resulting in high resistance) or SET(re-formed, resulting in lower resistance) by another voltage. Many current paths, rather than a single filament, are probably involved.[20]

A memory cell can be produced from the basic switching element in three different ways. In the simplest approach, the single memory element can be used as a basic memory cell, and inserted into a configuration in which parallel bitlines are crossed by perpendicular wordlines with the switching material placed between wordline and bitline at every cross-point. This configuration is called a cross-point cell. Since this architecture can lead to a large "sneak" parasitic current flowing through non-selected memory cells via neighboring cells, the cross-point array may have very slow read access. A selection element can be added to improve the situation, but this selection element consumes extra voltage and power. A series connection of a diode at every cross-point allows reverse biased, zero biased, or at least partially biased non-selected cells, leading to negligible sneak currents. This can be arranged in a similar compact manner as the basic cross-point cell. A transistor device (ideally a MOS transistor) can be added that eases cell selection and therefore gives the best random access time, at the price of increased area consumption.

For random access type memories, a transistor type architecture is preferred while the cross-point architecture and the diode architecture may enable vertically stacking memory layers and therefore are ideally suited for mass storage devices. The switching mechanism itself can be classified in different dimensions.

Polarity can be either binary or unary. Bipolar effects cause polarity to reverse when switching from low to high resistance (reset operation) compared to switching high to low (set operation). Unipolar switching leaves polarity unaffected, but uses different voltages.

Separately, the low resistive path can be either localized (filamentary) or homogeneous. Both effects can occur either throughout the entire distance between the electrodes or only in proximity to one of the electrodes. Filamentary and homogenous switching effects can be distinguished by measuring the area dependence of the low resistance state.[21]

Material systems for resistive memory cells[edit]

Multiple inorganic and organic material systems display thermal or ionic resistive switching effects. These can be grouped into the following categories:[21]

  • phase change chalcogenides such as Ge
    2
    Sb
    2
    Te
    5
    or AgInSbTe
  • binary transition metal oxides such as NiO or TiO
    2
  • perovskites such as Sr(Zr)TiO
    3
    or PCMO
  • solid-state electrolytes such as GeS, GeSe, SiO
    x
    or Cu
    2
    S
  • organic charge transfer complexes such as CuTCNQ
  • organic donor–acceptor systems such as Al AIDCN

Demonstrations[edit]

Papers at the IEDM Conference in 2007 suggested for the first time that RRAM exhibits lower programming currents than PRAM or MRAM without sacrificing programming performance, retention or endurance.[22] On April 30, 2008 HP announced that they had discovered the memristor, originally envisioned as a missing 4th fundamental circuit element by Chua in 1971. On July 8 they announced they would begin prototyping RRAM using their memristors.[23] At IEDM 2008, the highest performance RRAM technology to date was demonstrated by ITRI,[24] showing switching times less than 10 ns and currents less than 30 microamps. At IEDM 2010, ITRI again broke the speed record, showing <0.3 ns switching time, while also showing process and operation improvements to allow yield up to 100%.[25] IMEC presented updates of their RRAM program at the 2012 Symposia on VLSI Technology and Circuits, including a solution with a 500nA operating current.[26]

Future applications[edit]

Compared to PRAM, RRAM operates at a faster timescale (switching time can be less than 10 ns), while compared to MRAM, it has a simpler, smaller cell structure (less than 8F² MIM stack). A vertical 1D1R (one diode, one resistive switching device) integration can be used for crossbar memory structure to reduce the unit cell size to 4F² (F is the feature dimension).[27] Compared to flash memory and racetrack memory, a lower voltage is sufficient and hence it can be used in low power applications.

ITRI has shown that RRAM is scalable below 30 nm.[28] The motion of oxygen atoms is a key phenomenon for oxide-based RRAM;[29] one study indicated that oxygen motion may take place in regions as small as 2 nm.[30] It is believed that if a filament is responsible, it would not exhibit direct scaling with cell size.[31] Instead, the current compliance limit (set by an outside resistor, for example) could define the current-carrying capacity of the filament.[32]

A significant hurdle to realizing the potential of RRAM is the sneak path problem that occurs in larger passive arrays. In 2010, complementary resistive switching (CRS) was introduced as a possible solution to sneak-path current interference.[33] In the CRS approach, the information storing states are pairs of high and low resistance states (HRS/LRS and LRS/HRS) so that the overall resistance is always high, allowing for larger passive crossbar arrays.

A drawback to the initial CRS solution is the requirement for switching endurance caused by conventional destructive readout based on current measurements. A new approach for a nondestructive readout based on capacity measurement potentially lowers the requirements for both material endurance and power consumption.[34] Bi-layer structure is used to produce the nonlinearity in LRS to avoid the sneak path problem.[35] A single layer device exhibiting a strong nonlinear conduction in LRS was reported.[36] Another bi-layer structure was introduced for bipolar RRAM to improve the HRS and stability.[37]

References[edit]

  1. ^ U.S. Patent 6,531,371
  2. ^ U.S. Patent 7,292,469
  3. ^ U.S. Patent 6,867,996
  4. ^ U.S. Patent 7,157,750
  5. ^ U.S. Patent 7,067,865
  6. ^ U.S. Patent 6,946,702
  7. ^ U.S. Patent 6,870,755
  8. ^ Mellor, Chris (7 February 2012), Rambus drops $35m for Unity Semiconductor 
  9. ^ "the new microcontrollers with on-chip non-volatile memory ReRAM" (Press release). Panasonic. May 15, 2012. Retrieved May 16, 2012. 
  10. ^ "Next-gen storage wars: In the battle of RRAM vs 3D NAND flash, all of us are winners" (Press release). PC World. August 9, 2013. Retrieved January 28, 2014. 
  11. ^ A non-filamentary switching action in thermally grown silicon dioxide films. doi:10.1088/0508-3443/18/1/306.  edit
  12. ^ Resistance Switching Characteristics for Nonvolatile Memory Operation of Binary Metal Oxides. doi:10.1143/JJAP.46.2172.  edit
  13. ^ doi:10.1063/3701581
    This citation will be automatically completed in the next few minutes. You can jump the queue or expand by hand
  14. ^ Chua, L. O. (2011), "Resistance switching memories are memristors", Applied Physics A 102 (4): 765–783, Bibcode:2011ApPhA.102..765C, doi:10.1007/s00339-011-6264-9 
  15. ^ Mellor, Chris (10 October 2011), "HP and Hynix to produce the memristor goods by 2013", The Register, retrieved 2012-03-07 
  16. ^ Meuffels, P.; Soni, R. (2012), "Fundamental Issues and Problems in the Realization of Memristors", arXiv, arXiv:1207.7319, Bibcode:2012arXiv1207.7319M 
  17. ^ Di Ventra, Massimiliano; Pershin, Yuriy V. (2013). "On the physical properties of memristive, memcapacitive and meminductive systems". Nanotechnology 24 (25). arXiv:1302.7063. Bibcode:2013Nanot..24y5201D. doi:10.1088/0957-4484/24/25/255201. PMID 23708238. 
  18. ^ Valov, I.; Linn, E.; Tappertzhofen, S.; Schmelzer, S.; van den Hurk, J.; Lentz, F.; Waser, R. (2013). "Nanobatteries in redox-based resistive switches require extension of memristor theory". Nature Communications 4: 1771. doi:10.1038/ncomms2784. PMID 23612312.  edit
  19. ^ "the Foresight Institute » Blog Archive » Nanotechnology-based next generation memory nears mass production". Foresight.org. Retrieved 2014-08-13. 
  20. ^ doi:10.1063/1.2715002
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  21. ^ a b "Advanced Engineering Materials - Wiley Online Library". Aem-journal.com. Retrieved 2014-08-13. 
  22. ^ doi:10.1109/IEDM.2007.4419060
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  23. ^ EETimes.com - Memristors ready for prime time
  24. ^ H-Y. Lee et al., IEDM 2008.
  25. ^ H-Y. Lee et al., IEDM 2010.
  26. ^ L. Goux et al., 2012 Symp. on VLSI Tech. Dig. of Tech. Papers, 159 (2012).
  27. ^ Vertically integrated ZnO-Based 1D1R structure for resistive switching. doi:10.1088/0022-3727/46/14/145101.  edit
  28. ^ Y.-S. Chen et al., IEDM 2009.
  29. ^ New Non-Volatile Memory Workshop 2008, Hsinchu, Taiwan.
  30. ^ Nanoscale control of an interfacial metal–insulator transition at room temperature. doi:10.1038/nmat2136.  edit
  31. ^ I. G. Baek et al.,IEDM 2004.
  32. ^ Bistable Resistive Switching in Al2O3 Memory Thin Films. doi:10.1149/1.2750450.  edit
  33. ^ Complementary resistive switches for passive nanocrossbar memories. doi:10.1038/nmat2748.  edit
  34. ^ Capacity based nondestructive readout for complementary resistive switches. doi:10.1088/0957-4484/22/39/395203.  edit
  35. ^ Engineering nonlinearity into memristors for passive crossbar applications. doi:10.1063/1.3693392.  edit
  36. ^ Electrically tailored resistance switching in silicon oxide. doi:10.1088/0957-4484/23/45/455201.  edit
  37. ^ FeZnO-Based Resistive Switching Devices. doi:10.1007/s11664-012-2045-2.  edit