Template:Processor technologies: Difference between revisions

v t e CPU technologies
Architecture	Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit (NPU) Convolutional neural network Load/store architecture Register memory architecture Endianness FIFO Zero-copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Reconfigurable computing Cognitive computing Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Quantum computing Neuromorphic computing Optical computing Reversible computing Unconventional computing Hypercomputation Ternary computer Symmetric multiprocessing (SMP) Asymmetric multiprocessing (AMP) Cache hierarchy Memory hierarchy
ISA types	ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison
ISAs	x86 z/Architecture ARM MIPS Power Architecture (PowerPC) SPARC Mill Itanium (IA-64) Alpha Prism SuperH Clipper VAX Unicore PA-RISC MicroBlaze RISC-V
Word size	1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable
Execution	Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards
Parallel level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory
Multithreading	Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout
Flynn's taxonomy	SISD SIMD (SWAR) SIMT MISD MIMD SPMD Addressing mode
CPU performance	Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic Updates Per Second (SUPS) Performance per watt Orders of magnitude (computing) Cache performance measurement and metric
Core count	Single-core processor Multi-core processor Manycore processor
Types	Central processing unit (CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor (DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit (PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module (MCM) Chip stack multi-chip modules System on a chip (SoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip (PSoC) Network on a chip (NoC)
Components	Execution unit (EU) Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Load-store unit (LSU) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit (MMU) Input–output memory management unit (IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer (TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate Combinational logic Sequential logic Emitter-coupled logic (ECL) Transistor–transistor logic (TTL) Glue logic Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor
Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating
Hardware security	Non-executable memory (NX bit) Memory Protection Extensions (Intel MPX) Intel Secure Key Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology Trusted Platform Module (TPM) Secure cryptoprocessor Hardware security module Hengzhi chip
Related	History of general-purpose CPUs

@@ Line 23: / Line 23: @@
 * [[Von Neumann architecture|Von Neumann]]
 * [[Harvard architecture|Harvard]] ([[Modified Harvard architecture|modified]])
-* [[HIVE (Hierarchical Identify Verify Exploit)]]
 * [[Dataflow architecture|Dataflow]]
 * [[Transport triggered architecture|TTA]]
@@ Line 34: / Line 33: @@
 * [[Load/store architecture]]
 * [[Register memory architecture]]
-* [[Register register architecture]]
 * [[Endianness]]
 * [[FIFO (computing and electronics)|FIFO]]
@@ Line 56: / Line 54: @@
 * [[Analog computer|Analogous computing]]
 * [[Mechanical computer|Mechanical computing]]
-* [[Electric computer|Electric computing]]
 * [[Hybrid computer|Hybrid computing]]
 * [[Digital computer|Digital computing]]
@@ Line 97: / Line 94: @@
 * [[Power Architecture]] ([[PowerPC]])
 * [[SPARC]]
-* [[VISC architecture|VISC]]
 * [[Mill architecture|Mill]]
 * [[Itanium]] ([[IA-64]])
@@ Line 251: / Line 247: @@
 * [[Floating-point unit]] (FPU)
 * [[Load-store unit (computing)|Load-store unit]] (LSU)
-* [[Fixed-point unit]] (FXU)
-* [[Vector unit]] (VU)
 * [[Branch predictor]]
-* [[Branch execution unit]] (BEU)
-* [[Instruction Decoder]]
-* [[Instruction Scheduler]]
-* [[Instruction Fetch Unit]]
-* [[Instruction Dispatch Unit]]
-* [[Instruction Sequencing Unit]]
 * [[Reservation station|Unified Reservation Station]]
 * [[Barrel shifter]]
@@ Line 337: / Line 325: @@
 * [[Software Guard Extensions|Software Guard Extensions (Intel SGX)]]
 * [[Trusted Execution Technology]]
-* [[OmniShield]]
 * [[Trusted Platform Module]] (TPM)
 * [[Secure cryptoprocessor]]

Template:Processor technologies: Difference between revisions

Revision as of 06:04, 27 January 2018

See also