Parallel computing

The Cray-2 was the world's fastest computer from 1985 to 1989.

Parallel computing is a form of computing in which many instructions are carried out simultaneously. Parallel computing operates on the principle that large problems can almost always be divided into smaller ones, which may be carried out concurrently ("in parallel"). Parallel computing exists in several different forms: bit-level parallelism, instruction level parallelism, data parallelism, and task parallelism. It has been used for many years, mainly in high performance computing, but interest in it has become greater in recent years due to physical constraints preventing frequency scaling. Parallel computing has recently become the dominant paradigm in computer architecture, mainly in the form of multicore processors.

Parallel computer programs are harder to write than sequential ones, because concurrency introduces several new classes of potential software bugs, of which race conditions are the most common. Communication and synchronization between the different subtasks is typically one of the greatest barriers to getting good parallel program performance. In recent years, power consumption in parallel computers has also become a great concern. The speed up of a program as a result of parallelization is given by Amdahl's law.

Background

Traditionally, computer software has been written for serial computation. To solve a problem, an algorithm is constructed which produces a serial stream of instructions. These instructions are executed on a central processing unit on one computer. Only one instruction may execute at a given time - after that instruction is finished, the next is executed.

Parallel computing on the other hand uses multiple processing elements simultaneously to solve a problem. The problem is broken into parts which are independent so that each processing element can execute its part of the algorithm simultaneously with others. The processing elements can be diverse and include resources such as a single computer with multiple processors, a number of networked computers, specialized hardware or any combination of the above.

Frequency scaling was the dominant reason for computer performance increases from the mid 1980s until 2004. The total runtime of a program is proportional to the total number of instructions multiplied by the average time per instruction. Everything else constant, increasing the clock frequency decreases the average time it takes to execute an instruction. An increase in frequency thus decreases runtime for all computation-bounded programs.

However, power consumption in a chip is given by the equation $P=C\times V^{2}\times F$ where P is power, C is the capacitance being switched per clock cycle (proportional to the number of transistors whose inputs change), V is voltage, and F is the processor frequency (cycles per second). Increases in frequency thus increase the amount of power used in a processor. Increasing processor power consumption led ultimately to Intel's May 2004 cancellation of its Tejas and Jayhawk processors, which is generally cited as the end of frequency scaling as the dominant computer architecture paradigm.

Moore's Law is the empircal observation that transistor density in a microprocessor doubles every 18 to 24 months. Despite power issues, and repeated predictions of its end, Moore's law is still in effect. With the end of frequency scaling, these additional transistors (which are no longer used to facilitate frequency scaling) can be used to add extra hardware to facilitate parallel computing.

Amdahl's law and Gustafson's law

The performance of an algorithm on a parallel computing platform depends on parallelizing the algorithm to achieve performance so it is important to be aware of Amdahl's law, originally formulated by Gene Amdahl in the 1960's. It states that a small portion of the program which can’t be parallelized will limit the overall speedup available from parallelization. Any large math or engineering problem will typically consists of several parallelizable parts and several non-parallelizable (sequential) parts. This relationship is given by Amdahl's law:

$S={\frac {1}{(1-P)}}$

where S is the speedup of the program (as a factor of its original sequential runtime), and P is the fraction that is parallelizable. If the sequential portion of a program is 10% of the runtime, we can get no more than a 10x speedup, regardless of how many processors are added. This puts an upper bound on the usefulness of adding more parallel execution units.

A graphical representation of Amdahl's law. Assume that a task has two independent parts, A and B. B takes roughly 25% of the time of the whole computation. With effort, a programmer may be able to make this part 5 times faster, but this only reduces the time for the whole computation by a little. In contrast, one may need to perform less work to make part A be twice as fast. This will make the computation much faster than by optimizing part B, even though B got a greater speed-up, (5x versus 2x).

Gustafson's law is another law in computer engineering, closely related to Amdahl's law. Gustafson's law can be formulated as:

$S(P)=P-\alpha *(P-1)$

where P is the number of processors, S is the speedup, and $\alpha$ the non-parallelizable part of the process. Amdahl's law assumes a fixed-problem size and that the size of the sequential section is independent of the number of processors, whereas Gustafson's law does not make these assumptions.

Dependencies

Understanding data dependencies is one of the foundations of knowing how to implement parallel algorithms. No program can run quicker than the longest chain of dependent calculations (known as the critical path), since the fact that the calculations are dependent introduces an ordering of executions. Fortunately, most algorithms do not consist of a long chain of dependent calculations and little else, but instead there are many opportunities for executing independent calculations in parallel.

Let P_i and P_j be two program fragments. Bernstein's conditions describe when the two are independent and can be executed in parallel. Let I_i be all of the input variables to P_i and O_i the output variables, and likewise for P_j. P _i and P_j are independent if they satisfy

• $I_{j}\cap O_{i}=\emptyset$
• $I_{i}\cap O_{j}=\emptyset$
• $O_{i}\cap O_{j}=\emptyset$

Violation of the first condition introduces a flow dependency, corresponding to first statement producing a result used by the second statement. The second condition represents an anti-dependency, when the first statement overwrites a variable needed by the second expression. The third, and final condition q is an output dependency. When two variables write to the same location, the final output must be the one of the second statement.

For example, consider the following function:

1: function Dep(a, b)
2:    c := a·b
3:    d := 2·c
4: end function

Operation 3 in Dep(a,b) cannot be executed before (or even in parallel) operation 2, due to the fact that operation 3 uses a result from operation 2. It violates condition 1, and thus introduces a flow dependency.

1: function NoDep(a, b)
2:      c := a·b
3:      d := 2·b
4:      e := a+b
5: end function

In this example there are no dependencies between the instructions, so they can all be run in parallel.

Bernstein’s conditions do not allow memory to be shared between different processes. For that, some means of enforcing an ordering between accesses, such as semaphores, barriers or some other synchronization method is needed.

Race conditions, mutual exclusion, and synchronization

Subtasks in a parallel program are often called threads. Some parallel computer architectures use smaller, lightweight versions of threads known as fibers, while others use bigger versions known as processes. However, "threads" is generally accepted as a generic term for subtasks.

Threads will often need to update some variable that is shared between them. The instructions between the two programs may be interleaved in any order. For example, consider the following program

Thread A	Thread B
1A: Read variable V	1B: Read variable V
2A: Add 1 to variable V	2B: Add 1 to variable V
3A Write back to variable V	3B: Write back to variable V

If instruction 1B is executed between 1A and 3A, or if instruction 1A is executed between 1B and 3B, the program will produce incorrect data. This is known as a race condition. The programmer must use a lock to provide mutual exclusion. A lock is a programming language construct that allows one thread to take control of a variable and prevent other threads from reading or writing it, until that variable is unlocked. The thread holding the lock is free to execute its critical section (the section of a program that requires exclusive access to some variable), and unlock the data when it is finished.

Therefore, in order to guarantee correct program execution, the above program can be rewritten to use locks:

Thread A	Thread B
1A: Lock variable V	1B: Lock variable V
2A: Read variable V	2B: Read variable V
3A: Add 1 to variable V	3B: Add 1 to variable V
4A Write back to variable V	4B: Write back to variable V
5A: Unlock variable V	5B: Unlock variable V

One thread will successfully lock variable V, while the other thread will be locked out—unable to proceed until V is unlocked again. This guarantees correct execution of the program. Locks, while necessary to ensure correct program execution, can greatly slow down a program.

Locking multiple variables using non-atomic locks introduces the possibility of program deadlock. An atomic lock is a lock that locks multiple variables all-at-once. If it cannot lock all of them, it does not lock any of them. If two threads each need to lock the same two variables using non-atomic locks, it is possible that one thread will lock one of them and the second thread will lock the second variable. In such a case, neither thread can complete, and deadlock results.

Many parallel programs require that their subtasks act in synchrony. This requires the use of a barrier. Barriers are typically implemented using a software lock. One class of algorithms, known as lock-free and wait-free algorithms, avoid altogether the use of locks and barriers. However, this approach is generally difficult to implement and requires correctly designed data structures.

Fine-grained, coarse-grained, and embarrassing parallelism

Applications are often classified according to how often their subtasks need to synchronize or communicate with each other. An application exhibits fine-grained parallelism if its subtasks must communicate many times per second; it exhibits course-grained parallelism if they do not communicate many times per second, and it is embarrassingly parallel if they rarely or never have to communicate. Embarrassingly parallel applications are considered the easiest to parallelize.

Consistency models

Main article: Consistency model

Leslie Lamport first defined the concept of sequential consistency. Lamport is also well-known for his work in creating the LaTeX typesetting scheme.

Parallel programming languages and parallel computers must have a consistency model (also known as a memory model). The consistency model defines rules for how operations on computer memory occur and how results are produced.

One of the first consistency models was Leslie Lamport's sequential consistency model. Sequential consistency is the property of a parallel program that its parallel execution produces the same results as a sequential program. Specifically, a program is sequentially consistent if "...the results of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program."

Software transactional memory is a common type of consistency model. Software transactional memory borrows from database theory the concept of atomic transactions and applies them to memory accesses.

Mathematically, these models can be represented in a number of ways. Process calculus is the branch of mathematics dealing with concurrency. Process calculus can be subdivided into ambient calculus, calculus of communicating systems, and communicating sequential processes. Petri nets were an early attempt to codify the rules of consistency models. Dataflow theory later built upon these. Dataflow architectures were later created that physically implement the ideas of dataflow.

Flynn's taxonomy

Michael J Flynn created one of the earliest classification systems for parallel (and sequential) computers and programs, now known as Flynn's taxonomy. Flynn classified programs and computers by whether they were operating using a single or multiple sets of instructions, whether or not those instructions were using a single or multiple sets of data.

The single-instruction-single-data (SISD) classification is equivalent to an entirely sequential program. The single-instruction-multiple-data (SIMD) classification is analogous to doing the same operation repeatedly over a large data set. This is commonly done in signal processing applications. Multiple-instruction-single data (MISD) is a rarely used classification. While computer architectures to deal with this were devised (such as systolic arrays), few applications that fit this class materialized. Multiple-instruction-multiple-data (MIMD) programs are by far the most common type of parallel programs.

According to David A. Patterson and John L. Hennessy, "Some machines are hybrids of these categories, of course, but this classic model has survived because it is simple, easy to understand, and gives a good first approximation. It is also—perhaps because of its understandability—the most widely used scheme."

Types of parallelism

Bit-level parallelism

Main article: Bit-level parallelism

From the advent of very-large-scale integration (VLSI) computer chip fabrication technology in the 1970s until about 1986, advancements in computer architecture were done by doubling computer word size—the amount of information the processor can execute per cycle. Increasing the word size reduces the number of instructions the processor must execute in order to perform an operation on variables whose sizes are greater than the length of the word. For example, consider a case where an 8-bit processor must add two 16-bit integers. The processor must first add the 8 lower-order bits from each integer using the standard addition instruction, then add the 8 higher-order bits using an add-with-carry instruction and the carry bit from the lower order addition. Thus an 8 bit processor requires two instructions to complete a single operation, where a 16-bit processor would be able to complete the operation with single instruction.

Historically, 4-bit microprocessors were replaced with 8-bit, then 16-bit, then 32-bit microprocessors. This trend generally came to an end with the introduction of 32-bit processors, which has been a standard in general purpose computing for two decades. Only recently, with the advent of x86-64 architectures, have 64-bit processors become commonplace.

Instruction level parallelism

Main article: Instruction level parallelism

A computer program is, in essence, a stream of instructions executed by a processor. These instructions can be re-ordered and combined into groups which are then executed in parallel without changing the result of the program. This is known as instruction level parallelism. Advancements in instruction level parallelism dominated computer architecture from the mid-1980s until the mid-1990s.

A canonical five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back)

Modern processors have multi-stage instruction pipelines. Each stage in the pipeline corresponds to a different action the processor performs on that instruction in that stage. In other words, a processor with N pipeline stages can have up to N different instructions at different stages of completion. The canonical example of a pipelined processor is a RISC processor with five stages: instruction fetch, decode, execute, memory access, write back. The Pentium 4 processor had a 35-stage pipeline.

A five-stage pipelined superscalar processor, capable of issuing two instructions per cycle. It can have two instructions in each stage of the pipeline, for a total of up to ten instructions (shown in green) being simultaneously executed.

In addition to instruction level parallelism from pipelining, some processors can issue more than one instruction at a time. These are known as superscalar processors. Instructions can be grouped together only if there is no data dependency between them.

Scoreboarding and the Tomasulo algorithm (which is similar to scoreboarding but makes use of register renaming) are two of the most common techniques for implementing out-of-order execution and instruction level parallelism.

Data parallelism

Main article: Data parallelism

Data parallelism is parallelism inherent in program loops, which focuses on distributing the data across different computing nodes to be processed in parallel. "Parallelizing loops often leads to similar (not necessarily identical) operation sequences or functions being performed on elements of a large data structure." Many scientific and engineering applications exhibit data parallelism.

A loop-carried dependency is the property of a loop iteration that it depends on the output of one or more previous iterations. Loop carried dependencies prevent parallelization of loops. For example, consider the following pseudocode that computes the first few Fibonacci numbers:

1:    prev := 0
2:    cur := 1
3:    do:
4:       PREV := CUR
5:       CUR := CUR + PREV
6:    while (CUR < 10) 

This loop cannot be parallelized because CUR depends on itself and PREV, which are computed in each loop iteration. Since each loop iteration depends on the result of the previous iteration, they cannot be done in parallel.

As the size of a problem gets bigger, the amount of data-parallelism available usually does as well.

Task parallelism

Main article: Task parallelism

Task parallelism is the characteristic of a parallel program that "entirely different calculations can be performed on either the same or different sets of data". This contrasts with data parallelism, where the same calculation is being performed on the same or different sets of data. Task parallelism usually does not scale with the size of a problem.

Hardware

Memory and communication

Main memory in a parallel computer is either shared memory—shared between all processing elements in a single address space; or distributed memory—where each processing element has its own local address space. Distributed memory refers to the fact that the memory is logically distributed, but often implies that it is physically distributed as well. Distributed shared memory is a combination of the two approaches, where the processing element has its own local memory and access to the memory on non-local processors. Accesses to local memory are typically faster than accesses to non-local memory.

A logical view of a Non-Uniform Memory Access (NUMA) architecture. Processors in one directory can access that directory's memory with less latency than they can access memory in the other directory's memory.

Computer architectures in which all of main memory can be accessed with equal latency and bandwidth are known as Uniform Memory Access (UMA) systems. Typically, only a shared memory system (where the memory is not physically distributed) can achieve these. A system that does not have this property is known as a Non-Uniform Memory Access (NUMA) architecture. Distributed memory systems have non-uniform memory access.

Computer systems make use of caches—small, fast memories located close to the processor which store temporary copies of memory values. (Nearby in both the physical and logical sense.) Parallel computer systems have difficulties with caches that may store the same value in more than one location, creating the possibility of incorrect program execution. These computers require a cache coherency system, which keeps track of cached values and strategically purges them, thus ensuring correct program execution. Bus snooping is one of the most common methods for keeping track of which values are being accessed (and thus should be purged). Designing large, high-performance cache coherence systems is a very difficult problem in computer architecture. As a result, shared-memory computer architectures do not scale as well as distributed memory systems do.

The processor-processor and processor-memory communication can be implemented in hardware in a number of ways, including via shared (either multiported or multiplexed) memory, a crossbar switch, a shared bus or an interconnect network of a myriad of topologies including star, ring, tree, hypercube, fat hypercube (a hypercube with more than one processor at a node), an n-dimensional mesh, etc.

Parallel computers based on interconnect networks need to employ some kind of routing to enable passing of messages between nodes that are not directly connected. The communication medium used for communication between the processors is likely to be hierarchical in large multiprocessor machines.

Classes of parallel computers

Parallel computers can be classified roughly into classes according to the level at which the hardware supports parallelism. This is roughly analogous to the distance between basic computing nodes.

Note that these classifications are not mutually exclusive. For example, clusters of symmetric multiprocessors are relatively common.

Multicore computing

Main article: Multi-core (computing)

A multicore processor is a processor which includes multiple execution units ("cores"). Multicore processors differ from superscalar processors in that a superscalar processor can issue multiple instructions per cycle from one instruction stream (thread), whereas a multicore processor can issue multiple instructions per cycle from multiple instruction streams. Each core in a multicore processor can potentially be superscalar as well - that is, on every cycle, each core can issue multiple instructions from one instruction stream.

Simultaneous multithreading (of which Intel's HyperThreading is the best known) was an early form of pseudo-multicoreism. A processor capable of simultaneous multithreading has only one execution unit ("core"), but at times that execution unit would be idling (such as during a cache miss), it uses that execution unit to process a second thread.

Intel's Core and Core 2 processor families are Intel's first true multicore architectures. IBM's Cell microprocessor, designed for use in the Sony Playstation 3, is another prominent multicore processor.

Symmetric multiprocessing

Main article: Symmetric multiprocessing

A symmetric multiprocessor (SMP) is a computer system with multiple identical processors that share memory and connect via a bus. Bus contention prevents bus architectures from scaling. As a result, SMPs generally do not exceed 32 processors. "Because of the small size of the processors and the significant reduction in the requirements for bus bandwidth achieved by large caches, such symmetric multiprocessors are extremely cost-effective, provided that a sufficient amount of memory bandwidth exists"

Distributed computing

A distributed computer (also known as a distributed memory multiprocessor) is a distributed memory computer system where the processing elements are connected by a network. Distributed computers are highly scalable.

Cluster computing

Main article: Computer cluster

A Beowulf cluster

A cluster is a group of loosely coupled computers that work together closely so that in many respects they can be viewed as though they are a single computer. Clusters are composed of multiple standalone machines connected by a network. While machines in a cluster do not have to be symmetric, load balancing is more difficult if they are not.

The most common type of cluster is the Beowulf cluster, which is a cluster implemented on multiple identical commercial off-the-shelf computers connected with a TCP/IP Ethernet local area network. Beowulf technology was originally developed by Thomas Sterling and Donald Becker.

The vast majority of the TOP500 supercomputers are clusters.

Massive parallel processing

Main article: Massive parallel processing

A cabinet from Blue Gene/L, ranked as the fastest supercomputer in the world according to the TOP500 rankings. Blue Gene/L is a massively parallel processor.

A massively parallel processor (MPP) is a single computer with a very large number of networked processors. MPPs have many of the same characteristics as clusters, but they are usually larger, typically having "far more" than 100 processors. In an MPP, "each CPU contains its own memory and copy of the operating system and application. Each subsystem communicates with the others via a high-speed interconnect."

Blue Gene/L, the fastest supercomputer in the world according to the TOP500 ranking, is an MPP.

Grid computing

Main article: Grid computing

Grid computing is the most distributed form of parallel computing. Grid computing makes use of computers many miles apart, connected by the Internet, to work on a given problem. Because of the low bandwidth and extremely high latency available on the Internet, typically grid computing deals only with embarrassingly parallel problems. Many grid computing applications have been created, of which SETI@home and Folding@Home are best known examples.

Most grid computing applications use middleware—software that operates between the operating system and the application, which manages network resources and standardizes the software interface for grid computing applications. The most common grid computing middleware is the Berkeley Open Infrastructure for Network Computing (BOINC). Often, grid computing software makes use of "spare cycles", doing computations at times when a computer is idling.

Specialized parallel computers

Within parallel computing, there are specialized parallel devices which remain niche areas of interest. While not domain specific, they tend to be applicable only to a few classes of parallel problems.

Reconfigurable computing with field-programmable gate arrays

Reconfigurable computing is the use of a field-programmable gate array (FPGA) as a co-processor to a general-purpose computer. An FPGA is, in essence, a computer chip which can rewire itself for a given task.

FPGAs can be programmed with hardware description languages such as VHDL or Verilog. However, programming in these languages can be tedious. A number of vendors have created C to HDL languages, that attempt to emulate the syntax and/or semantics of the C programming language, which most programmers are familiar with. The best known C to HDL languages are Mitrion-C, Impulse C, DIME-C, and Handel-C.

AMD's decision to open its HyperTransport technology to third party vendors has become the enabling technology for high performance reconfigurable computing. According to Michael R. D'Amour, CEO of DRC Computer Corporation, "when we first walked into AMD, they called us 'the socket stealers.' Now they call us their partners."

GPGPU with graphics processing units

Main article: GPGPU

General-purpose computing on graphics processing units (GPGPU) is a fairly recent trend in computer engineering research. GPUs are co-processors that have been heavily optimized for computer graphics processing. Computer graphics processing is a field dominated by data parallel operations—particularly linear algebra matrix operations.

CUDA is the dominant GPGPU a programming language. CUDA was developed by NVIDIA for use on NVIDIA graphics cards. Other GPU programming languages are BrookGPU, PeakStream, and RapidMind.

NVIDIA Tesla is NVIDIA's first dedicated GPGPU card.

Application-specific integrated circuits

Main article: Application-specific integrated circuit

A number of Application-specific integrated circuit (ASIC) approaches have been devised for dealing with parallel applications.

Because an ASIC is (by definition) specific to a given application, it can be fully optimized for that application. As a result, for a given application, an ASIC tends to outperform a general purpose computer. However, ASICs are created by X-ray lithography. This process requires a mask, which can be extremely expensive. A single mask can cost over a million United States dollars. (The smaller the transistors required for the chip, the more expensive the mask will be.) Meanwhile, performance increases in general purpose computing as a result of Moore's Law tend to wipe out these gains in only one or two chip generations. Such high initial cost, and the tendency to be overtaken by Moore's law-driven general purpose computing, render ASICs unfeasible for most parallel computing applications.

Vector processors

Main article: Vector processor

The Cray-1 is the most famous vector processor.

A vector processor is a CPU or computer system that can execute the same instruction on large sets of data. "Vector processors have high-level operations that work on linear arrays of numbers or vectors. An example vector operation is $A=B\times C$ where A, B, and C are each 64-element vectors of 64-bit floating point numbers. They are closely related to Flynn's SIMD classification.

Cray computers became famous for their vector processing computers in the 1970s and 1980s. However, vector processors—both as CPUs and as full computer systems—have generally disappeared. Modern processor instruction sets do include some vector processing instructions, such as with AltiVec and Streaming SIMD Extensions (SSE).

Software

A number of concurrent programming languages, libraries, APIs, and parallel programming models have been created for programming parallel computers.

These can generally be divided into classes based on the assumptions they make about the underlying memory architecture—shared memory, distributed memory, or shared distributed memory. Shared memory programming languages communicate by means of manipulating shared memory variables. Distributed memory uses message passing. POSIX Threads and OpenMP are two of most widely used shared memory APIs, whereas Message Passing Interface (MPI) is the most widely used message passing system API.

Automatic parallelization

Main article: Automatic parallelization

Automatic parallelization of a sequential program by a compiler is the "holy grail" of parallel computing. Despite decades of work by compiler researchers, automatic parallelization has had only limited success.

Mainstream parallel programming languages remain either explicitly parallel or (at best) partially implicit with the programmer giving the compiler directives for parallelization. A few fully implicit parallel programming languages exist - SISAL, Parallel Haskell, and (for FPGAs) Mitrion-C - but these are niche languages that are not widely used.

Application checkpointing

Main article: Application checkpointing

The larger and more complex a computer gets, the more can go wrong, and the smaller the mean time between failures becomes. Application checkpointing is a technique whereby the computer system takes a "snapshot" of the application—a record of all current resource allocations and variable states, akin to a core dump. This information can then be used to restore the program if the computer should fail. Application checkpointing means that the program will only have to restart from its last checkpoint, rather than the beginning. For an application that may take months, this is critically important. Application checkpointing may also be used to facilitate process migration.

History

ILLIAC IV, "perhaps the most infamous of Supercomputers"

The origins of true (MIMD) parallelism go back to Federico Luigi, Conte Menabrea and his "Sketch of the Analytic Engine Invented by Charles Babbage." IBM introduced the 704 in 1954, through the project in which Gene Amdahl was one of the principal architects. It became the first commercially available computer to use fully automatic floating point arithmetic commands. In 1958, IBM researchers John Cocke and Daniel Slotnick discussed the use of parallelism in numerical calculations for the first time. Burroughs Corporation introduced the D825 in 1962, a four-processor computer that accessed up to 16 memory modules through a crossbar switch. In 1967, Amdahl and Slotnick published a debate about the feasibility of parallel processing at American Federation of Information Processing Societies Conference. Amdahl's argument about limits to parallelism became called as "Amdahl's Law".

In 1969, US company Honeywell introduced its first Multics system, a symmetric multiprocessor system capable of running up to eight processors in parallel. C.mmp, a 1970s multi-processor project at Carnegie Mellon University, was "among the first multiprocessors with more than a few processors." "The first bus-connected multi-processor with snooping caches was the Synapse N+1 in 1984".

SIMD parallel computers can be traced back to the 1970s. The motivation behind early SIMD computers was to amortize the gate delay of the processor's control unit over multiple instructions. Earlier, in 1964, Slotnick had proposed building a massively-parallel computer for the Lawrence Livermore National Laboratory. His design was funded by the US Air Force, which materialized as the earliest SIMD parallel computing effort, ILLIAC IV. Key to its design was a fairly high parallelism with up to 256 processors, used to allow the machine to work on large data sets in what would later be known as vector processing. However, ILLIAC IV was called "the most infamous of Supercomputers" because the project was built only one-fourth to completion, but took 11 years to build and cost almost four times its original estimated cost. When it was finally ready to run its first real application in 1976, it was outperformed by existing commercial supercomputers like the Cray-1.

External links

• Template:Dmoz
• Lawrence Livermore National Laboratory: Introduction to Parallel Computing
• Designing and Building Parallel Programs, by Ian Foster
• Internet Parallel Computing Archive
• National HPCC Software Exchange
• Parallel processing topic area at IEEE Distributed Computing Online
• Parallel Computing Works Free On-line Book
• Frontiers of Supercomputing Free On-line Book Covering topics like algorithms and industrial applications