Jump to content

Zilog Z8

From Wikipedia, the free encyclopedia

This is an old revision of this page, as edited by Jerryobject (talk | contribs) at 08:16, 30 March 2020 (Updates: template, 'Image:' > 'File:'. MOS:FIRSTABBReviations define before WP:ABBRs. WP:LINKs: updates, adds, fix-cut needless WP:PIPEs (WP:NOPIPEs). WP:BADEMPHASIS quote marks > WP:ITALICs. WP:SLASH > comma+space. Small WP:EoS WP:TERSE WP:COPYEDITs: clarify, WP:FORMAL. WP:EXTernal link parameterless > WP:REFerence WP:CITation, parameters: adds, fills. Template:Official website add. WP:NAVBOX update.). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Zilog Z8 processor
Zilog Z8 (Super-8 family)

The Zilog Z8 is a microcontroller architecture, originally introduced in 1979, which today also includes the Z8 Encore!, eZ8 Encore!,[1] eZ8 Encore! XP, and eZ8 Encore! MC families.

Signifying features of the architecture are up to 4,096 fast on-chip registers which may be used as accumulators, pointers, or as ordinary random-access memory (RAM). A 16-bit address space for between 1 kibibyte (KB) and 64 KB of either programmable read-only memory (PROM, OTP), read-only memory (ROM), or flash memory, are used to store code and constants, and there is a second 16-bit address space which can be used for large applications.

On chip peripherals include analog-to-digital converter (A/D), Serial Peripheral Interface (SPI) bus and Inter-Integrated Circuit (I²C) channels, IrDA encoders/decoders etc. There are versions with from 8 up to 80 pins, housed in dual in-line package (PDIP), Quad Flat No-leads package (MicroLeadFrame, MLF), small outline integrated circuit (SOIC), Shrink Small-Outline Package (SSOP), and low profile Quad Flat Package (LQFP). The eZ8 Encore! series can be programmed and debugged through a single pin serial communication interface.

The basic architecture, a modified (non-strict) Harvard architecture, is technically very different from the Zilog Z80. Despite this, the instruction set and assembly language syntax are quite similar to other Zilog processors: Load/store operations use the same LD mnemonic (no MOV or MOVEs), typifying instructions such as DJNZ, are the same, and so on.

An integrated development environment (IDE) named Zilog Developer's Studio (ZDS) can be downloaded from Zilog's website including an assembler. The edition of ZDS II targeting Z8 Encore! and newer derivatives also includes a free compiler claiming ANSI C89 compliance.

Primary competitors include the somewhat similar[2] Microchip Technology PIC family, and all Intel 8051 descendants. Also more traditional von Neumann architecture based single chip microcontrollers may be regarded as competitors, such as the Motorola 6800, 6809 based Motorola 68HC11, the Hitachi H8 family, and Z80-derivatives, such as Toshiba TLCS-870, to name only a few.

Product line

  • ROMless: Models without integrated ROM
  • ROM: Models with integrated ROM
  • BASIC: Models with integrated BASIC interpreter and debugger in ROM
  • OTP: Models with integrated programmable read-only memory (OTP ROM)
  • Low Voltage: Working voltage run as low as 2V
  • GP: General purpose microcontroller
  • Encore!: Integrated flash-based memory
  • Encore! XP: Encore! with sensors
  • Encore! MC (Motor Control): Motor control applications

Emulators

JTCEMU is a free software (GNU General Public License (GPL) version 3) Z8 emulator written in Java for Linux, Windows, and macOS.[3]

Second sources

Notes

  1. ^ The "Encore!" products contains the newer eZ8 core which is 2-3 times as clock cycle efficient as the original Z8 core.
  2. ^ The PIC and the 8051 are using Harvard architectures as well, but in a more rigid manner.
  3. ^ Müller, Jens (26 July 2011). "JTCEMU: JU+TE-Computer-Emulator". Jens Müller's homepage. Retrieved 2020-03-30.

References

  • Grehan, Rick (September 1994). "Processors Proliferate". Byte.
Retrieved from "https://en.wikipedia.org/w/index.php?title=Zilog_Z8&oldid=948125453"