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ARM9

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ARM9T
General information
Designed byARM Holdings
Architecture and classification
MicroarchitectureARMv4T
Instruction setARM (32-bit),
Thumb (16-bit)
ARM9E
Architecture and classification
MicroarchitectureARMv5TE
Instruction setARM (32-bit),
Thumb (16-bit)
ARM9EJ
Architecture and classification
MicroarchitectureARMv5TEJ
Instruction setARM (32-bit),
Thumb (16-bit),
Jazelle (8-bit)

ARM9 is a group of older 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use.[1] The ARM9 core family consists of ARM9TDMI, ARM940T, ARM9E-S, ARM966E-S, ARM920T, ARM922T, ARM946E-S, ARM9EJ-S, ARM926EJ-S, ARM968E-S, ARM996HS. Since ARM9 cores were released from 1998 to 2006, they are no longer recommended for new IC designs, instead ARM Cortex-A, ARM Cortex-M , ARM Cortex-R cores are preferred.[1]

Overview

See also: ARM architecture and List of ARM cores

With this design generation, ARM moved from a von Neumann architecture (Princeton architecture) to a (modified; meaning split cache) Harvard architecture with separate instruction and data buses (and caches), significantly increasing its potential speed.[2] Most silicon chips integrating these cores will package them as modified Harvard architecture chips, combining the two address buses on the other side of separated CPU caches and tightly coupled memories.

There are two subfamilies, implementing different ARM architecture versions.

Differences from ARM7 cores

Key improvements over ARM7 cores, enabled by spending more transistors, include:[3]

  • Decreased heat production and lower overheating risk.
  • Clock frequency improvements. Shifting from a three-stage pipeline to a five-stage one lets the clock speed be approximately doubled, on the same silicon fabrication process.
  • Cycle count improvements. Many unmodified ARM7 binaries were measured as taking about 30% fewer cycles to execute on ARM9 cores. Key improvements include:
    • Faster loads and stores; many instructions now cost just one cycle. This is helped by both the modified Harvard architecture (reducing bus and cache contention) and the new pipeline stages.
    • Exposing pipeline interlocks, enabling compiler optimizations to reduce blockage between stages.

Additionally, some ARM9 cores incorporate "Enhanced DSP" instructions, such as a multiply-accumulate, to support more efficient implementations of digital signal processing algorithms.

Switching to from a von Neumann architecture entailed a non-unified cache, so that instruction fetches do not evict data (and vice versa). ARM9 cores have separate data and address bus signals, which chip designers use in various ways. In most cases they connect at least part of the address space in von Neumann style, used for both instructions and data, usually to an AHB interconnect connecting to a DRAM interface and an External Bus Interface usable with NOR flash memory. Such hybrids are no longer pure Harvard architecture processors.

ARM license

ARM Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Cores

Year ARM9 Cores
1998 ARM9TDMI
1998 ARM940T
1999 ARM9E-S
1999 ARM966E-S
2000 ARM920T
2000 ARM922T
2000 ARM946E-S
2001 ARM9EJ-S
2001 ARM926EJ-S
2004 ARM968E-S
2006 ARM996HS

The ARM MPCore family of multicore processors support software written using either the asymmetric (AMP) or symmetric (SMP) multiprocessor programming paradigms. For AMP development, each central processing unit within the MPCore may be viewed as an independent processor and as such can follow traditional single processor development strategies.[4]

ARM9TDMI

ARM9TDMI is a successor to the popular ARM7TDMI core, and is also based on the ARMv4T architecture. Cores based on it support both 32-bit ARM and 16-bit Thumb instruction sets and include:

  • ARM920T with 16 KB each of I/D cache and an MMU
  • ARM922T with 8 KB each of I/D cache and an MMU
  • ARM940T with cache and a Memory Protection Unit (MPU)

ARM9E-S and ARM9EJ-S

ARM9E, and its ARM9EJ sibling, implement the basic ARM9TDMI pipeline, but add support for the ARMv5TE architecture, which includes some DSP-esque instruction set extensions. In addition, the multiplier unit width has been doubled, halving the time required for most multiplication operations. They support 32-bit, 16-bit, and sometimes 8-bit instruction sets.

  • ARM926EJ-S with ARM Jazelle technology, which enables the direct execution of 8-bit Java bytecode in hardware, and an MMU
  • ARM946
  • ARM966
  • ARM968

Chips

Nintendo DSi has a chip with an ARM9 and ARM7 cores
Lego Mindstorms EV3 brick has an ARM9 TI Sitara AM1x
ARM920T
ARM926EJ-S
ARM966E-S
Unreferenced ARM9 core

Documentation

The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer and documents from CPU core vendor (ARM Holdings).

A typical top-down documentation tree is: high-level marketing slides, datasheet for the exact physical chip, a detailed reference manual that describes common peripherals and other aspects of physical chips within the same series, reference manual for the exact ARM core processor within the chip, reference manual for the ARM architecture of the core which includes detailed description of all instruction sets.

Documentation tree (top to bottom)
  1. IC manufacturer marketing slides.
  2. IC manufacturer datasheets.
  3. IC manufacturer reference manuals.
  4. ARM core reference manuals.
  5. ARM architecture reference manuals.

IC manufacturer has additional documents, including: evaluation board user manuals, application notes, getting started with development software, software library documents, errata, and more.

See also

See also: List of ARM Cortex-M development tools

References

  1. ^ a b ARM9 Family Webpage; ARM Holdings.
  2. ^ Furber, Steve. ARM System-on-Chip Architecture. p. 344. ISBN 0201675196.
  3. ^ "Performance of the ARM9TDMI and ARM9E-S cores compared to the ARM7TDMI core", Issue 1.0, dated 9 February 2000, ARM Ltd.
  4. ^ "MPCore Sample Code". Archived from the original on 11 April 2015.
  5. ^ a b Atmel Legacy ARM-Based Solutions; Atmel.
  6. ^ SAM9G ARM9 Microcontrollers; Atmel.
  7. ^ SAM9M ARM9 Microcontrollers; Microchip.
  8. ^ SAM9N/CN ARM9 Microcontrollers; Atmel.
  9. ^ SAM9R/RL ARM9 Microcontrollers; Atmel.
  10. ^ SAM9X ARM9 Microcontrollers; Atmel.
  11. ^ SAM9XE ARM9 Microcontrollers; Atmel.
  12. ^ i.MX28 Applications Processors; NXP.
  13. ^ "LPC3100/200 Series: Arm9™-based microcontrollers|NXP". www.nxp.com. Retrieved 2018-07-27.
  14. ^ https://csrc.nist.gov/csrc/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp2574.pdf
  15. ^ STR9 ARM9 Microcontrollers; STMicroelectronics.
  16. ^ "NS9210/NS9215 32-bit NET+ARM Processor Family" (PDF). Digi International.
Wikimedia Commons has media related to ARM9.
ARM9 official documents
Quick Reference Cards
  • Instructions: Thumb (1), ARM and Thumb-2 (2), Vector Floating Point (3)
  • Opcodes: Thumb (1, 2), ARM (3, 4), GNU Assembler Directives 5.
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