Camera Link is a serial communication protocol standard designed for computer vision applications based on the National Semiconductor interface Channel-link. It was designed for the purpose of standardizing scientific and industrial video products including cameras, cables and frame grabbers. The standard is maintained and administered by the Automated Imaging Association or AIA, the global machine vision industry's trade group.
Camera Link uses one to three Channel-link transceiver chips with four links at 7 serial bits each. At a minimum, Camera Link uses 28 bits to represent up to 24 bits of pixel data and 3 bits for video sync signals, leaving one spare bit. The video sync bits are Data Valid, Frame Valid, and Line Valid. The data are serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The receiver accepts the four LVDS data streams and LVDS clock, and then drives the 28 bits and a clock to the board. The camera link standard calls for these 28 bits to be transmitted over 4 serialized differential pairs with a serialization factor of 7. The parallel data clock is transmitted with the data. Typically a 7× clock must be generated by a PLL or SERDES block in order to transmit or receive the serialized video. To deserialize the data, a shift register and counter may be employed. The shift register catches each of the serialized bits, one at a time, then registers the data out into the parallel clock domain - once the data counter has reached its terminal value.
Camera Link comes in several variants which differ in the amount of data that can be transferred. Some of them require two cables for transmission.
The "Base" Camera Link configuration carries signals over a single connector/cable. The cable used is a MDR ("Mini D Ribbon") 26-pin Male Plug Connector, optimized by 3M for the LVDS signal. In addition to the 5 LVDS pairs transmitting the serialized video data (24 bits of data and 4 framing/enable bits), the connector also carries 4 LVDS discrete control signals and 2 LVDS asynchronous serial communication channels for communicating with the camera. At the maximum chipset operating frequency (85 MHz), the base configuration yields a video data throughput of 2.04 Gbit/s (255 MB/s).
The Camera Link specification includes higher-bandwidth configurations that provide additional video data paths over a second connector/cable. The "Medium" configuration doubles the video bandwidth, adding 24 bits of data and the same 4 framing/enable bits present in the "Base" configuration. This yields a 48-bit wide video data path capable of throughput up to 4.08 Gbit/s (510 MB/s). The "Full" configuration adds another 16-bits to the data path, resulting in a 64-bit wide video path that can carry 5.44Gbit/s (680 MB/s).
Some camera and data acquisition hardware manufacturers have extended the bandwidth of the interface beyond the limits imposed by the Camera Link interface specification. These formats extend the width of the "Full" configuration by utilizing 8 unused bits and reassigning the 8 redundant framing/enable bits to produce a data path width of up to 80 bits over two connectors/cables, which further increases the video bandwidth. A consensus has emerged in the industry about the 80-bit variant, and compatible cameras and frame grabbers are marketed with the term "Camera Link Deca". However, some manufacturers use the term "Extended Full" to refer to Deca configuration, and still others retain use of the term Camera Link Full while referring to Full Deca. The 80-bit video path can carry 6.8 Gbit/s (850 MB/s).
The image below shows the relative signal timing of the clock and one data line of one of the Channel Link transceivers used for Camera Link transmissions. Data words start in the middle of the high phase of the clock, and the most significant bit is transmitted first.
The bits of pixel values are not assigned to serial transmitters in order, but are permutated in a complicated way, as shown in the following figure:
WARNING: Do not rely on the diagram below. For example, it shows "F" (FVAL) on "X3", but the Camera Link specification puts this signal on TX/RX25, and then the DS90CR288A chip puts TxIN25 on TxOUT2 (aka X2), not X3. Furthermore, the bit numbers used do not correspond to the Camera Link specification (v2.0 Feb10 2012 final doesn't number 0-21 for base or 0-69 for full), or the DS90CR288A chip specification (which doesn't number this way either). Do not even assume that bits 0-7 correspond to Camera Link Base port bits A0-A7. They don't. Instead, combine the two references mentioned earlier to get a mapping. While the diagram below might be correct for some other device or chipset, it is not correct for the DS90CR288A under any reasonable assumption of bit or channel numbering.
The upper half of this figure is only relevant for the Medium and Full configurations which require two physical interfaces and two cables. The two rectangles in the middle represent the cables, with the connector pins of each signal printed at either side.
To the left of the transceivers, the list of pixel data bits transmitted over that Channel Link is printed, from LSB to MSB. The characters L, F and D refer to the Line Sync, Frame Sync and Data Valid bits, respectively. The underscore represents an unused spare bit. It remains to be said how pixel data bits are assigned to the bits 0 to 71 used in the figure. For grey-scale pixels, this is a trivial one-to-one mapping; for colour pixels with a multiple of 8 bits per colour, the colours are simply concatenated in the order red, green and blue (from LSB to MSB). For 12-bit RGB data, the lower 8 bits of each colour are assigned to data bits 0-7,16-23,32-39; the higher 4 bits of each colour to bits 8-11,12-15,40-43.
Cables and connectors
The standard prescribes 26-pin Miniature Delta Ribbon connectors (MDR-26) for use with Camera Link; the shrunk variant SDR-26 is allowed since standard version 1.2. The connector pin assignments are shown in the large figure in the previous section. The connector pinout is the following:
Matching differential pairs are deliberately located at opposite sides of the connector, and at different connector sides at the different ends of the cable. This prevents skew due to the connector being mounted perpendicularly on a PCB.
Camera Link cables are shielded twisted pair cables. The standard specifies that differential pairs must be individually shielded, and the cable as a whole must have two shields. Some companies save costs by not shielding the two serial interface signal pairs, which carry slower signals than the camera data; these cables have one camera end and one grabber end and may not be reversed, and cannot be used as a second cable in a Medium or Full configuration.
Interface Standard Specifications
The Camera Link standard is maintained by the AIA. The introduction of the Camera Link Interface Standard (1.0) was released in October 2000. Revision 1.1 was adopted in January 2004, with expanded software function support. The standard committee adopted version 1.2 in January 2007, introducing mini SDR ("Shrunk D Ribbon") connectors (SDR-26) and power over Camera Link (POCL). Annex D of revision 1.2 adds mechanical and electrical descriptions to the standard, especially cable performance. Annex E of revision 1.2 lists requirements of POCL equipment. Camera Link 2.0 was released in November 2011.
- Channel Link
- Automated Imaging Association
- GigE vision
- List of device bandwidths
- Low-voltage differential signaling (LVDS)
- Specifications of the Camera Link Interface Standard for Digital Cameras and Frame Grabbers, Version 1.1 Automated Imaging Association, Jan 2004
- Short Overview of the Camera Link Technology by camera manufacturer Basler
- A technical description of the CameraLink interface
- NI PCIe 1433 Manual
- MC13xx User Manual