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ARC (processor)

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ARC (Argonaut RISC Core) embedded processors are a family of 32-bit CPUs originally designed by ARC International. They are widely used in SoC devices for storage, home, mobile, automotive, and Internet of Things applications. ARC processors have been licensed by more than 200 organizations and are shipped in more than 1.5 Billion products per year.[1]

ARC processors are now part of the Synopsys DesignWare series, and can be optimized for a wide range of uses. Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements. The ARC processors are also extendable, allowing designers to add their own custom instructions that can significantly increase performance or reduce power consumption.

ARC processors are RISC processors, and employ the 16-/32-bit ARCompact instruction set architecture that provides good performance and code density for embedded and host SoC applications. The processors are synthesizable and can be implemented in any foundry or process, and are supported by a complete suite of development tools.[2]

Configuration of the ARC processors occurs at design time, using the ARChitect processor configurator.[3] The core was designed to be extensible. Unlike most embedded microprocessors, extra instructions, registers and functionality can be added, in a Lego-block kind of manner. Customers analyse the task, break down the operations, and then choose the appropriate extensions, or develop their own to create their own custom microprocessor. They might optimise for speed, energy efficiency or code density. Extensions can include for example, an MMU, a fast multiplier–accumulator, a USB Host, a viterbi path decoder, or a user's proprietary RTL functions.

The ARC concept was developed initially within Argonaut Games through a series of 3D pipeline development projects starting with the Super FX chip for the Super Nintendo Entertainment System. In 1995, Argonaut was split into Argonaut Technologies Limited (ATL) which had a variety of technology projects and Argonaut Software Limited (ASL). At the start of 1996, the General Manager of Argonaut, John Edelson, started reducing ATL projects such as BRender and motion capture and investing in the development of the ARC concept. In 1997, following investment by Apax Partners, ATL became ARC International and totally independent from Argonaut Games. Prior to the IPO on the London Stock Exchange underwritten by Goldman Sachs and 5 other investment banks, three related technology companies were acquired: Metaware in Santa Cruz, California (development and modeling software);, VAutomation in Nashua, New Hampshire (peripheral semiconductor IP), and Precise Software in Nepean, Canada (RTOS).

Families

Synopsys's DesignWare ARC Processor IP includes the ARC HS, ARC EM, ARC 700 and ARC 600 families of 32-bit processor cores, as well as the ARC AS211 and AS221 audio processors and optimized software audio codecs. ARC processor cores are based on a flexible and proven industry-standard instruction set architecture (ISA) with features optimized for a broad range of embedded and deeply embedded applications. The ARC processors feature:

  • Performance-efficient designs deliver maximum performance while consuming a minimum amount of power and silicon area
  • Highly configurable processors can be performance- and power-optimized for each instance on an SoC while sharing a common programming model
  • Extensible ISA supports user-defined custom instructions, enabling integration of users' proprietary hardware to accelerate application-specific tasks
  • Streamlined system integration through the ability to closely couple memory and directly map peripherals to the core, reduce system latency and cost

ARC HS Processors

The ARC HS Family processors can be clocked at speeds up to 2.2 GHz while consuming less than 80 mW[1] of power on typical 28 nm processes. The family includes the HS34, HS36 and HS38 Processors. The HS34 supports Close Coupled Memory (CCM) while the HS36 adds up to 64KB of instruction and data caches, and the HS38 adds a full memory management unit. The processors are designed for high performance with power efficiency (DMIPS/mW) and area efficiency (DMIPS/mm2), for embedded applications with very high speed data and signal processing requirements. The HS Processors are available in dual-core and quad-core versions for applications that require even higher performance.

ARC EM Processors

The ARC EM Family includes the ARC EM4, EM6, and the DSP-enhanced EM5D, EM7D, EM9D and EM11D processors. The ARC EM4, EM5D and EM7D processors support instruction and data CCMs and the EM6, EM7D, and EM11D add instruction and data caches. The ultra-compact cores feature efficient code density, small size and very low power consumption, for power-critical and area-sensitive embedded and deeply embedded applications. The EM5D and EM7D processors are used in always-on voice-activated and sensor processing applications. The EM9D and EM11D with XY (or multi-bank) support target applications with more DSP requirements such as combined voice, speech and audio applications. The dynamic power consumption of the ARC EM processors can be as low as 3 μW/MHz, and they are well-suited for wearable devices and battery-powered applications. The ARC EM processors with integrated hardware safety features and optional Safety Enhancement Package (SEP) are ISO 26262 ASIL-D ready for automotive safety applications. Additional options include an Enhanced Security Package for creating trusted execution environments and prevention of tampering, CryptoPack for accelerating cryptographic algorithms, a memory protection unit, a tightly coupled microDMA, and floating point unit.

Sensor IP Subsystem

The DesignWare Sensor IP Subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more power-efficient processing of the sensor data. The fully configurable subsystem consists of a DesignWare ARC EM4 32-bit processor, serial digital interfaces, analog-to-digital converter interfaces, hardware accelerators, a comprehensive software library of DSP functions and I/O software drivers. The DesignWare Sensor IP Subsystem provides designers with a complete and pre-verified solution that meets the requirements of a broad range of applications such as such as intelligent sensors, sensor fusion, and sensor hub increasingly prevalent in automotive, mobile, industrial and smart energy markets.

ARC 700 Processors

The ARC 700 Family includes the ARC 710D, ARC 725D and ARC 770D Processors. The processors, which can run at more than 1.2 GHz in a 28 nm process, are designed for embedded applications and tasks where high performance and low power consumption is required. The ARC 700 Family supports single-cycle CCMs for instructions and data, as well as configurable I-cache and D-cache. Optional DSP and floating point capabilities enable designers to address a wide range of signal processing requirements with a single processor, simplifying the design, lowering silicon-area and enabling faster debug of the chip. The ARC 770D features a full memory management unit (MMU) and is designed specifically to improve execution performance for embedded applications running Linux.

ARC 600 Processors

The ARC 600 Family includes the ARC 610D and ARC 625D Processors. The ARC 600 Processors target embedded applications where enhanced DSP performance with small size and low power consumption is required. The addition of support for an advanced XY memory architecture enables efficient DSP processing with fast access to algorithm coefficients stored in dedicated X and Y memories. This enables low power and efficient processing of audio data and other digital signals and information. The ARC 600 Family includes flexible memory options such as single-cycle CCMs for instructions and data, as well as configurable I-cache and D-cache. The optional floating point extension enables additional signal processing capabilities for single- and double-precision floating point calculations with minimal additional area and power consumption.

ARC AS200 Audio Processors

The ARC AS200 Family includes the AS211SFX and AS221BD Audio Processors. These processors feature powerful audio DSP capabilities and are supported with a broad portfolio of certified audio codecs and post-processing software from a range of popular standards including Dolby®, DTS®, Microsoft®, and SRS. The AS211SFX Audio Processor is designed for consumer, portable and mobile applications including portable audio players, digital cameras, media players and digital TV where lowest power and smallest area are required. The AS221BD Processor is a dual-core processor designed for high-performance, multi-channel HD audio and Blu-ray Disc™ applications.

SoundWave Audio Subsystem

The DesignWare SoundWave Audio Subsystem provides designers with a complete, pre-verified audio subsystem consisting of hardware, software and prototyping for integration into SoC designs. It consists of DesignWare 32-bit ARC audio processors, standard digital interfaces, analog audio codecs, and a complete, ready-to-use software environment that seamlessly plugs into the host application and includes a comprehensive library of software audio codecs that support the latest formats from Dolby, DTS and SRS. Supporting 2.1 to 7.1 audio streams at 24-bit precision, the SoundWave Audio Subsystem meets the demanding performance requirements of today's audio applications such as digital TVs, set-top boxes, Blu-ray Disc, speaker bars, media players, portable audio and tablets.

Extensions and additional ARC processor options

To further optimize the processor for specific applications, a family of ARC extensions and options is available, including ARC XY Advanced DSP, ARC Floating Point, ARC Real-Time Trace and ARC Secure.[4]

Software development

Software toolchains

To accelerate the SoC development cycle, Synopsys's ARC Processor IP is supported by a complete and integrated development tool suite, including tools for configuration, software development and simulation. This enables ARC users to efficiently build, debug, profile and optimize their embedded software applications for ARC, while the available processor models makes it possible to get an early start on software development prior to hardware availability.

The ARC MetaWare Development Toolkit contains all of the components needed to support the development, debugging and optimization of embedded applications for ARC processors. The compiler and debugger are integrated in the Eclipse-based MetaWare Integrated Development Environment (IDE), and the Toolkit also comes with a base version of the nSIM Instruction Set Simulator.

In addition, Synopsys's DesignWare ARC processor cores are supported by the latest open-source GNU toolchain, including the GNU Compiler Collection (gcc), GNU Debugger (gdb), libraries and utilities.

Simulators

Synopsys offers a variety of simulation products spanning automatically-generated, cycle-accurate simulators to fast, functional instruction set simulators (ISS). Synopsys's simulation products enable software development prior to silicon being available.

The DesignWare ARC nSIM Pro Simulator is primarily used for software development and debugging. It can operate as a very fast ISS and it also has a mode that provides near cycle-accurate simulation. This mode, available for certain cores, can be used to optimize important software routines to improve efficiency.

DesignWare ARC xCAM is a 100% cycle-accurate simulator that is primarily used for hardware verification, but it can also be used to do final optimizations of critical software routines. The xCAM model is automatically generated from the processor configuration and can be used to evaluate different hardware scenarios.

Operating systems

To support applications that require fast, real-time response, Synopsys offers the MQX RTOS. MQX is a small, real-time kernel that occupies a small memory footprint and supports fast context switch times. ARC processor cores with Memory Management Units (MMUs) are supported by Linux, and Synopsys maintains and optimizes the Linux kernel to run on these ARC processor cores. The Linux kernel was originally ported to ARC processors in 2006.[5] The ARC port is part of the official release from kernel.org.

ARC Software Development Platforms

The DesignWare ARC AXS101 Software Development Platform is a complete, standalone platform enabling software development, code porting, software debugging and system analysis. It consists of an ARC AXC001 CPU Card mounted on an ARC Software Development Platform Mainboard. The CPU Card has an associated software package of pre-built operating systems, drivers and examples. Readily licensable DesignWare IP has been used to build the ARC Software Development Platform, giving the system a rich set of peripherals that can also be implemented in an SoC. The ARC Software Development Platform can easily be combined with the Synopsys HAPS FPGA-based Prototyping Solution to enable system prototyping and additional extension interfaces, such as five Digilent Pmod compatible connectors, support the integration of other custom and commercially available hardware extensions.

ARC EM Starter Kit

The ARC EM Starter Kit is a low-cost, versatile solution enabling rapid software development, code porting, software debugging, and system analysis for ARC EM4 and EM6 Processors. The kit consists of a hardware platform of pre-installed FPGA images of two ARC EM4 and two ARC EM6 configurations with peripherals, and a software package that includes the MQX real-time operating system (RTOS) in binary format, peripheral drivers, and application code examples.

References

  1. ^ a b "Overcoming the power/performance paradox in processor IP". techdesignforums.com. Retrieved 13 August 2014.
  2. ^ "Accelerating Development of Performance-Efficient SoCs". synopsys.com. Retrieved 13 August 2014.
  3. ^ "ARChitect Processor Configurator". Arc.com. Retrieved 2 March 2014.
  4. ^ "DesignWare ARC Processor Portfolio" (PDF). Synopsys.com. Retrieved 2 March 2014.
  5. ^ Oral presentation from Vineet Gupta at ELC Europe 2012. http://elceurope2012.sched.org/event/1c0bdd2422c6894bad83a6435a48469d with slideshow available at https://raw.github.com/vineetgarc/publish/master/ELCE-2012-ARC-Linux.pdf

Further reading

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