I3C (bus)

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I3C bus
Venn Diagram of I3C Heritage
Type Serial communication bus
Production history
Designer MIPI Alliance
Sensor Working Group
Designed 2016; 7 years ago (2016)
Hot pluggable Yes
Signal CMOS
Data signal Open-drain or Push/Pull
Width 2 wires [data + clock]

12.5 Mbit/s (SDR, standard), 25 Mbit/s (DDR), 33 Mbit/s (ternary),
legacy I²C rates
400 Kbits/s (FM),

Mbit/s (FM+)
Protocol Serial, half-duplex

I3C is a specification[1] to enable communication between computer chips by defining the electrical connection between the chips and signaling patterns to be used. Short for "Improved Inter Integrated Circuit",[2] the standard defines the electrical connection between the chips to be a two wire, shared (multidrop), serial data bus, one wire (SCL) being used as a clock to define the sampling times, the other wire (SDA) being used as a data line whose voltage can be sampled. The standard defines a signalling protocol in which multiple chips can control communication and thereby act as the bus controller.

The I3C specification takes its name from, uses the same electrical connections as, and allows some backward compatibility with, the I²C bus, a de facto standard for inter-chip communication, widely used for low-speed peripherals and sensors in computer systems. The I3C standard is designed to retain some backward compatibility with the I²C system, notably allowing designs where existing I²C devices can be connected to an I3C bus but still have the bus able to switch to a higher data rate for communication at higher speeds between compliant I3C devices. The I3C standard thereby combines the advantage of the simple, two wire I²C architecture with the higher communication speeds common to more complicated buses such as the Serial Peripheral Interface (SPI).

The I3C standard was developed as a collaborative effort between electronics and computer related companies under auspices of the Mobile Industry Processor Interface Alliance (MIPI Alliance). The I3C standard was first released to the public at the end of 2017,[3][4] although access requires the disclosure of private information. Google and Intel have backed I3C as a sensor interface standard for Internet of things (IoT) devices.[5]


Goals of the MIPI Sensor Working Group effort were first announced in November 2014 at the MEMS Executive Congress in Scottsdale AZ.[6]

Electronic design automation tool vendors including Cadence,[7] Synopsys[8] and Silvaco[9] have released controller IP blocks and associated verification software for the implementation of the I3C bus in new integrated circuit designs.

In December 2016, Lattice Semiconductor integrated I3C support into its new FPGA known as an iCE40 UltraPlus.[10]

In 2017, Qualcomm announced the Snapdragon 845 mobile SOC with integrated I3C controller support.[11][failed verification]

In December 2017, the I3C 1.0 specification was released for public review.[5][12] At about the same time, a Linux kernel patch introducing support for I3C was proposed by Boris Brezillon.[13]

In 2021, DDR5 has introduced I3C.

In June 2022, Renesas Electronics introduced the first I3C Intelligent switch products.[14]


Prior to public release of the specification, a substantial amount of general information about it has been published in the form of slides from the 2016 MIPI DevCon.[15] The goals for this interface were based on a survey of MIPI member organizations and MEMS Industry Group (MIG) members. The results of this survey have been made public.[16]

I3C v1.0[edit]

The initial I3C design sought to improve over I²C in the following ways:[17]

  • Two-pin interface that is a superset of the I²C standard. Legacy I²C target devices can be connected to the newer bus.
  • Low-power and space efficient design intended for mobile devices (smartphones and IoT devices.)
  • In-band interrupts over the serial bus rather than requiring separate pins. In I²C, interrupts from peripheral devices typically require an additional non-shared pin per package.
  • Standard Data Rate (SDR) throughput between 10 and 12.5 Mbit/s using CMOS I/O levels.
  • High Data Rate (HDR) modes permitting multiple bits per clock cycle. These support throughput comparable to SPI while requiring only a fraction of I²C Fast Mode power.[18]
  • A standardized set of common command codes
  • Command queue support
  • Error Detection and Recovery (parity check in SDR mode and 5 bit CRC for HDR modes)
  • Dynamic address assignment (DAA) for I3C targets, while still supporting static addresses for I²C legacy devices
  • I3C traffic is invisible for legacy I²C devices when equipped with I²C spike filters, achieved by SCL HIGH times of less than 50 ns
  • Hot-join (some devices on the bus may be powered on/off during operation)
  • Multi-controller operation with a well-defined protocol for hand-off between controllers

I3C Basic Specification[edit]

After making the I3C 1.0 standard publicly accessible, the organization subsequently published the I3C Basic specification, a subset intended to be implementable by non-member organizations under a RAND-Z licence. I3C Basic allows royalty-free implementation of I3C, and is intended for organizations that may view MIPI membership as a barrier for adoption. The basic version includes many of the protocol innovations in I3C 1.0, but lacks some of the potentially more difficult-to-implement ones such as the optional high data rate (HDR) modes like DDR. None the less the default SDR mode at up to 12.5 Mbit/s is a major speed/capacity improvement over I²C.[19]

I3C v1.1[edit]

Published in December 2019, this specification is only available to MIPI members.

I3C v1.1.1[edit]

Published in June 2021, it has deprecated the terms "master/slave" and now uses the updated normative terms "controller/target." The technical definitions of such devices, and their roles on an I3C bus, remain unchanged.


Signal pins[edit]

I3C uses same two signal pins as I²C, referred to as SCL (serial clock) and SDA (serial data). The primary difference is that I²C operates them as open-drain outputs at all times, so its speed is limited by the resultant slow signal rise time. I3C uses open-drain mode when necessary for compatibility, but switches to push-pull outputs whenever possible, and includes protocol changes to make it possible more often than in I²C.

  • SCL is a conventional digital clock signal, driven with a push-pull output by the current bus controller during data transfers. (Clock stretching, a frequently used I²C feature, is not supported.) In transactions involving I²C target devices, this clock signal generally has a duty cycle of approximately 50%, but when communicating with known I3C targets, the bus controller may switch to a higher frequency and/or alter the duty cycle so the SCL high period is limited to at most 40 ns.
  • SDA carries the serial data stream, which may be driven by either controller or target, but is driven at a rate determined by the controller's SCL signal. For compatibility with the I²C protocol, each transaction begins with SDA operating as an open-drain output, which limits the transmission speed. For messages addressed to an I3C target, the SDA driver mode switches to push-pull after the first few bits in the transaction, allowing the clock to be further increased up to 12.5 MHz. This medium-speed feature is called standard data rate (SDR) mode.

Generally, SDA is changed just after the falling edge of SCL, and the resultant value is received on the following rising edge. When the controller hands SDA over to the target, it likewise does so on the falling edge of SCL. However, when the target is handing back control of SDA to the controller (e.g. after acknowledging its address before a write), it releases SDA on the rising edge of SCL, and the controller is responsible for holding the received value for the duration of SCL high. (Because the controller drives SCL, it will see the rising edge first, so there will be a brief period of overlap when both are driving SDA, but as they are both driving the same value, no bus contention occurs.)


All communications in I²C and I3C requires framing for synchronization. Within a frame, changes on the SDA line should always occur while SCL is in the low state, so that SDA can be considered stable on the low-to-high transition of SCL. Violations of this general rule are used for framing (at least in legacy and standard data rate modes).

Between data frames, the bus controller holds SCL high, in effect stopping the clock, and SDA drivers are in a high-impedance state, permitting a pull-up resistor to float it to high. A high-to-low transition of SDA while SCL is high is known as a START symbol, and signals the beginning a new data frame. A low-to-high transition on SDA while SCL is high is the STOP symbol, ending a data frame.

A START without a preceding STOP, called a "repeated START", may be used to end one message and begin another within a single bus transaction.

In I²C, the START symbol is usually generated by a bus controller, but in I3C, even target devices may pull SDA low to indicate they want to start a frame. This is used to implement some advanced I3C features, such as in-band interrupts, multi-controller support, and hot-joins. After the start, the bus controller restarts the clock by driving SCL, and begins the bus arbitration process.

Ninth bit[edit]

Like I²C, I3C uses 9 clock cycles to send each 8-bit byte. However, the 9th cycle is used differently. I²C uses the last cycle for an acknowledgement sent in the opposite direction to the first 8 bits. I3C operates the same way for the first (address) byte of each message, and for I²C-compatible messages, but when communicating with I3C targets, message bytes after the first use the 9th bit as an odd parity bit on writes, and an end-of-data flag on reads.

Writes may be terminated only by the controller.

Either the controller or the target may terminate a read. The target sets SDA low to indicate that no more data is available; the controller responds by taking over SDA and generating a STOP or repeated START. To allow a read to continue, the target drives SDA high while SCL is low before the 9th bit, but lets SDA float (open-drain) while SCL is high. The controller may drive SDA low (a repeated START condition) at this time to abort the read.

Bus arbitration[edit]

At the start of a frame, several devices may contend for use of the bus, and the bus arbitration process serves to select which device obtains control of the SDA line. In both I²C and I3C, bus arbitration is done with the SDA line in open-drain mode, which allows devices transmitting a binary 0 (low) to override devices transmitting a binary 1. Contending devices monitor the SDA line while driving it in open-drain mode. Whenever a device detects a low condition (0 bit) on SDA while transmitting a high (1 bit), it has lost arbitration and must cease contending until the next transaction begins.

Each transaction begins with the target address, and the implementation gives priority to lower-numbered target addresses. The difference is that I²C has no limit on how long arbitration can last (in the rare but legal situation of several devices contending to send a message to the same device, the contention will not be detected until after the address byte). I3C, however, guarantees that arbitration will be complete no later than the end of the first byte. This allows push-pull drivers and faster clock rates to be used the great majority of the time.

This is done in several ways:

  • I3C supports multiple controllers, but they are not symmetrical; one is the current controller and responsible for generating the clock. Other devices sending a message on the bus (in-band interrupts or secondary controllers wishing use of the bus) must arbitrate using their own address before sending any other data. Thus, no two legal bus messages share the same first byte except if the controller and another device are simultaneously communicating with each other.
  • I3C, like I²C, allows multiple messages per transaction separated with "repeated START" symbols. Arbitration is per-transaction, so these subsequent messages are never subject to arbitration.
  • Most I3C controller transactions begin with the reserved address 0x7E(11111102). As this has a lower priority than any I3C device, once it has passed arbitration, the controller knows that no other device is contending for the bus.
  • As a special case, if I3C devices are assigned low addresses (I3C supports dynamic, controller-controlled address assignment), then as soon as the 0x7E address has won arbitration for enough leading bits to distinguish it from any assigned address, the controller knows that arbitration is complete and it may switch to push-pull operation on SDA. If all assigned addresses are less than 0x40, this is after the first bit. If all addresses are less than 0x60, this is after the second bit, and so on.
  • In the case described above wherein the current controller begins a transaction with the address of a device which is itself contending for use of the bus, both will transmit their address bytes successfully. However, each will expect the other to acknowledge the address (by pulling SDA low) for the following acknowledge bit. Consequently, neither will, and both will observe the lack of acknowledgement. In this case, the message is not sent, but the controller wins arbitration: it may send a repeated start, followed by a retry which will be successful.

Common command codes[edit]

A write addressed to the reserved address 0x7E is used to perform a number of special operations in I3C. All I3C devices must receive and interpret writes to this address in addition to their individual addresses.

First of all, a write consisting of just the address byte and no data bytes has no effect on I3C targets, but may be used to simplify I3C arbitration. As described above, this prefix may speed up arbitration (if the controller supports the optimization of switching to push-pull mid-byte), and it simplifies the controller by avoiding a slightly tricky arbitration case.

If the write is followed by a data byte, the byte encodes a "common command code", a standardized I3C operation. Command codes 0–0x7F are broadcast commands addressed to all I3C targets. They may be followed by additional, command-specific parameters. Command codes 0x80–0xFE are direct commands addressed to individual targets. These are followed by a series of repeated STARTs and writes or reads to specific targets.

While a direct command is in effect, per-target writes or reads convey command-specific parameters. This operation is in lieu of target's normal response to an I3C message. One direct command may be followed by multiple per-target messages, each preceded by a repeated START. This special mode ends at the end of the transaction (STOP symbol) or the next message addressed to 0x7E.

Some command codes exist in both broadcast and direct forms. For example, the commands to enable or disable in-band interrupts may be sent to individual targets or broadcast to all. Commands to get parameters from a target (for example the GETHDRCAP command to ask a device which high-data-rate modes it supports) only exist in direct form.

Device classes[edit]

On an I3C bus in its default (SDR) mode, four different classes of devices can be supported:

  • I3C Main Controller
  • I3C Secondary Controller
  • I3C Target
  • I²C Target (legacy devices)

High Data Rate (HDR) options[edit]

Each I3C bus transaction begins in SDR mode, but the I3C controller may issue an "Enter HDR" CCC broadcast command which tells all I3C targets that the transaction will continue in a specified HDR mode. I3C targets which do not support HDR may then ignore bus traffic until they see a specific "HDR exit" sequence which informs them it is time to listen to the bus again. (The controller knows which targets support HDR so will never attempt to use HDR to communicate with a target which does not support it.)

Some HDR modes are also compatible with I²C devices if the I²C devices have a 50 ns spike filter on the SCL line; that is, they will ignore a high level on the SCL line which lasts less than 50 ns. This is required by the I²C specification, but not universally implemented, and not all implementations ignore frequently repeated spikes,[20] so I3C HDR compatibility must be verified. The compatible HDR modes use SCL pulses of at most 45 ns so that I²C devices will ignore them.

The HDR-DDR mode uses double data rate signalling with a 12.5 MHz clock to achieve a 25 Mbit/s raw data rate (20 Mbit/s effective). This requires changing the SDA line while SCK is high, a violation of the I²C protocol, but I²C devices will not see the brief high-going pulse on SCL and thus not notice the violation.

The HDR-TSP and HDR-TSL modes use one of three symbols as ternary digits (trits):

  1. A transition of both SDA and SCL (received within 12.8 ns of each other),
  2. A transition of SCL only, or
  3. A transition of SDA only.

Two bytes plus two parity bits (18 bits total) are broken into six 3-bit triplets, and each triplet is encoded as two trits. Sent at 25 Mtrit/s, this achieves a 33.3 Mbit/s effective data rate.

The trit pair consisting of two transitions of SDA only is not used to encode data, and is instead used for framing, to mark the end of an HDR sequence. Although this limits the maximum time between SCL transitions to three trit times, that exceeds the 50 ns limit for legacy I²C devices, so HDR-TSP (ternary symbol, pure) mode may only be used on a bus without legacy I²C devices.

To permit buses including I²C devices (with a spike filter), the HDR-TSL (ternary symbol, legacy) mode must be used. This maintains I²C compatibility by trit stuffing: after any rising edge on SCL, if the following trit is not 0, a 1 trit (transition on SCL only) is inserted by the sender, and ignored by the receiver. This ensures that SCL is never high for more than one trit time.

I²C features not supported in I3C[edit]

  • Pull-up resistors are provided by the I3C controller. External pull-up resistors are no longer needed.
  • Clock Stretching – devices are expected to be fast enough to operate at bus speed. The I3C controller is the sole clock source.
  • I²C Extended (10-bit) Addresses. All devices on an I3C bus are addressed by a 7-bit address. Native I3C devices have a unique 48-bit address which is used only during dynamic address assignments.


  1. ^ "MIPI I3C and I3C Basic". mipi.org. 2017-01-06.
  2. ^ "I3C and I3C Basic Frequently Asked Questions | MIPI". www.mipi.org. Retrieved 2022-08-29.
  3. ^ "MIPI Alliance opens access to its MIPI I3C Sensor Interface Specification". 2017-12-14.
  4. ^ "MIPI Alliance releases MIPI I3C sensor-interface specification". www.evaluationengineering.com.
  5. ^ a b "MIPI makes market push for I3C sensor interface". 2017-12-14.
  6. ^ "MEMS/Sensor Interface I3C Rocks". 2014-11-12.
  7. ^ "IP | Cadence". Retrieved 2023-08-11.
  8. ^ "VC Verification IP for MIPI I3C". www.synopsys.com.
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  10. ^ "Lattice gives iCE40 more power, I/O and memory". 2016-12-12.
  11. ^ "Qualcomm SDM845 SoC | Integrated LTE Application Processor based on Snapdragon 845 | Qualcomm". www.qualcomm.com. Retrieved 2023-08-11.
  12. ^ "MIPI I3C". mipi.org. 2017-01-06.
  13. ^ "LKML: Boris Brezillon: [PATCH v2 0/7] Add the I3C subsystem". lkml.org.
  14. ^ "Renesas Unveils Industry's First I3C Intelligent Switch Family for Next Generation Server, Storage and Communications Systems | Renesas". www.renesas.com. Retrieved 2023-08-11.
  15. ^ "MIPI I3C Sensor Sessions at MIPI DevCon2016". resources.mipi.org. MIPI Alliance Inc.
  16. ^ http://mipi.org/sites/default/files/MIPI%20+%20MIG%20Member%20Sensor%20Interface%20Survey%20Results%20final.pdf[dead link]
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  18. ^ "MIPI DevCon 2016: MIPI I3C High Data Rate Modes". MIPI Alliance. 2016-09-23.
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  20. ^ "8-Kbit serial I2C bus EEPROM data sheet" (PDF). STMicroelectronics. October 2017. p. 27. DocID 023924 Rev 6. Archived (PDF) from the original on 2019-10-18. Retrieved 2019-11-19.

Further reading[edit]

External links[edit]