KOMDIV-64
| General information | |
|---|---|
| Launched | 2007 |
| Designed by | NIISI |
| Performance | |
| Max. CPU clock rate | 200 MHz to 1 GHz |
| Architecture and classification | |
| Technology node | 65 nm to 0.35 μm |
| Instruction set | MIPS IV |
| Physical specifications | |
| Cores |
|
The KOMDIV-64 (Russian: КОМДИВ-64) is a family of 64-bit microprocessors developed by the Scientific Research Institute of System Development (NIISI) of the Russian Academy of Sciences and manufactured by TSMC, UMC, GlobalFoundries, and X-Fab.[1] The KOMDIV-64 processors are intended primarily for industrial and high-performance computing applications.
These microprocessors implement the MIPS IV instruction set architecture (ISA).
Overview
| Designation | Cores | Production start (year) | Process (nm) | Clock rate (MHz) | Remarks | |
|---|---|---|---|---|---|---|
| Russian | English | |||||
| 1990ВМ3Т | 1990VM3T | 1 | 2008 ? | 350 | ? | [2][3][4] |
| 1890ВМ5Ф | 1890VM5F | 1 | 2007 ? | 350 | 350 | [2][3][4] |
| 1890ВМ6Я | 1890VM6Ya | 1 | 2011 | 180 | 270 | [2][3][4][5] |
| 1890ВМ7Я | 1890VM7Ya | 1 | 2011 | 180 | 200 | [2][3][4][6] |
| 1890ВМ8Я | 1890VM8Ya | 2 | 2015 | 65 | 800 | [2][4][7] |
| 1890ВМ9Я | 1890VM9Ya | 2 | 2016 | 65 | 1000 | [2][4] |
| 1907BM028 | 1907VM028 | 1 | 2016 | 250 | 150 | rad-hard[2][4][8] |
Details
1990VM3T
1890VM5F
- 0.35 μm CMOS process
- 16 KB L1 instruction cache, 16 KB L1 data cache, 256 KB L2 cache
- in-order, dual-issue superscalar; 5-stage integer pipeline, 7-stage floating point pipeline
- 26.6 million transistors
- compatible with PMC-Sierra RM7000
- performance: 0.68 dhrystones/MHz, 1.03 whetstones/MHz, 1.09 coremarks/MHz[9]
1890VM6Ya
- 0.18 μm CMOS process
- 16 KB L1 instruction cache, 16 KB L1 data cache, 256 KB L2 cache
- 680-pin BGA
- System-on-a-chip (SoC) including a PCI controller, 5 64-bit timers, RapidIO, Ethernet 100/10 Mbit/s, USB 2.0, I²C
- performance: 0.90 dhrystones/MHz, 1.32 whetstones/MHz, 1.47 coremarks/MHz[9]
1890VM7Ya
- 0.18 μm CMOS process
- 16 KB L1 instruction cache, 16 KB L1 data cache, 32 KB general-purpose SRAM
- 680-pin BGA
- System-on-a-chip (SoC) including a PCI controller, 3 64-bit timers, RapidIO, I²C, SPI, 128-bit DSP with 4 cores and 64 KB RAM per core
1890VM8Ya
- 65 nm CMOS process
- 32 KB L1 instruction cache, 16 KB L1 data cache, 512 KB L2 cache
- 1294-pin BGA
- System-on-a-chip (SoC) including a PCI controller, 5 64-bit timers, RapidIO, Ethernet 1000/100/10 Mbit/s, USB 2.0, I²C, SPI, SATA 3.0
- production start in 2015 at TSMC[4]
1890VM9Ya
- 65 nm CMOS process
- dual core, clock rate 1 GHz
- 1294-pin BGA
- System-on-a-chip (SoC) including RapidIO, Ethernet 1000 Mbit/s, USB 2.0, SATA 3.0
1907VM028
- 0.25 μm Silicon on Insulator (SOI) CMOS process
- 128 KB L2 cache
- 675-pin BGA
- System-on-a-chip (SoC) including RapidIO, Ethernet, PCI, I²C
See also
References
- ^ "Отделение разработки вычислительных систем" [Computer systems development branch] (in Russian). Moscow: NIISI. Retrieved 9 September 2016.
- ^ a b c d e f g "Разработка СБИС - Развитие микропроцессоров с архитектурой КОМДИВ" [VLSI development - Development of microprocessors using the KOMDIV architecture] (in Russian). Moscow: NIISI. Retrieved 6 September 2016.
- ^ a b c d "Микросхемы вычислительных средств, включая микропроцессоры, микроЭВМ, цифровые процессоры обработки сигналов и контроллеры" [Integrated circuits for computing devices, including microprocessors, microcomputers, digital signal processors, and controllers] (in Russian). Promelektronika VPK. Archived from the original on 28 March 2017. Retrieved 25 October 2017.
{{cite web}}: Unknown parameter|deadurl=ignored (|url-status=suggested) (help) - ^ a b c d e f g h "Изделия отечественного производства" [Domestic products] (in Russian). Moscow: AO "ENPO SPELS". Retrieved 1 September 2016.
- ^ "Микросхема 1890ВМ6Я / 1890ВМ6АЯ / 1890ВМ6БЯ" [Integrated Circuit 1890VM6Ya / 1890VM6AYa / 1890VM6BYa] (PDF) (in Russian). Moscow: NIISI. Retrieved 12 September 2016.
- ^ "Микросхема 1890ВМ7Я" [Integrated Circuit 1890VM7Ya] (PDF) (in Russian). Moscow: NIISI. Retrieved 12 September 2016.
- ^ "Микросхема 1890ВМ8Я" [Integrated Circuit 1890VM8Ya] (PDF) (in Russian). Moscow: NIISI. Retrieved 13 September 2016.
- ^ "Микросхема 1907ВМ028, 1907ВМ02Н4" [Integrated Circuit 1907VM028, 1907VM02N4] (PDF) (in Russian). Moscow: NIISI. Retrieved 24 March 2017.
- ^ a b Чибисов, Петр Александрович (28 September 2012). "Запуск ОС Linux как этап функционального тестирования микропроцессоров" [Launch of the Linux OS as a stage of the functional testing of microprocessors] (in Russian). NIISI. pp. 12–14. Retrieved 13 April 2017.