Subtractor

In electronics, a subtractor – a digital circuit that performs subtraction of numbers – can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with an adder, in the general case of calculations on multi-bit numbers, three bits are involved in performing the subtraction for each bit of the difference: the minuend ($X_{i}$), subtrahend ($Y_{i}$), and a borrow in from the previous (less significant) bit order position ($B_{i}$). The outputs are the difference bit ($D_{i}$) and borrow bit $B_{i+1}$. The subtractor is best understood by considering that the subtrahend and both borrow bits have negative weights, whereas the X and D bits are positive. The operation performed by the subtractor is to rewrite $X_{i}-Y_{i}-B_{i}$ (which can take the values -2, -1, 0, or 1) as the sum $-2B_{i+1}+D_{i}$.

$D_{i}=X_{}\oplus Y_{i}\oplus B_{i}$

$B_{i+1}=X_{i}<(Y_{i}+B_{i})$,

where ⊕ represents exclusive or.

Subtractors are usually implemented within a binary adder for only a small cost when using the standard two's complement notation, by providing an addition/subtraction selector to the carry-in and to invert the second operand.

$-B={\bar {B}}+1$ (definition of two's complement notation)

${\begin{alignedat}{2}A-B&=A+(-B)\\&=A+{\bar {B}}+1\\\end{alignedat}}$

Half subtractor

Figure 1: Logic diagram for a half subtractor

The half subtractors can be designed through the combinational Boolean logic circuits ^[2] as shown in Figure 1 and 2.The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend $X$ and subtrahend $Y$ and two outputs the difference $D$ and borrow out $B_{\text{out}}$. The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, $B_{\text{out}}=1$ when $X<Y$. Since $X$ and $Y$ are bits, $B_{\text{out}}=1$ if and only if $X=0$ and $Y=1$. An important point worth mentioning is that the half subtractor diagram aside implements $X-Y$ and not $Y-X$ since $B_{\text{out}}$ on the diagram is given by

$B_{\text{out}}={\overline {X}}\cdot Y$.

This is an important distinction to make since subtraction itself is not commutative, but the difference bit $D$ is calculated using an XOR gate which is commutative.

Figure 2: Half-subtractor using NAND gate only.

The truth table for the half subtractor is:

Inputs		Outputs
X	Y	D	Bout
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

Using the table above and a Karnaugh map, we find the following logic equations for $D$ and $B_{\text{out}}$:

$D=X\oplus Y$

$B_{\text{out}}={\overline {X}}\cdot Y$.

Consequently, a simplified half-subtract circuit, advantageously avoiding crossed traces in particular as well as a negate gate is:

      X ── XOR ─┬─────── |X-Y|,  is 0 if X equals Y, 1 otherwise
         ┌──┘   └──┐  
      Y ─┴─────── AND ── borrow, is 1 if Y > X, 0 otherwise

where lines to the right are outputs and others (from the top, bottom or left) are inputs.

Full subtractor

The full subtractor is a combinational circuit which is used to perform subtraction of three input bits: the minuend $X$, subtrahend $Y$, and borrow in $B_{\text{in}}$. The full subtractor generates two output bits: the difference $D$ and borrow out $B_{\text{out}}$. $B_{\text{in}}$ is set when the previous digit is borrowed from $X$. Thus, $B_{\text{in}}$ is also subtracted from $X$ as well as the subtrahend $Y$. Or in symbols: $X-Y-B_{\text{in}}$. Like the half subtractor, the full subtractor generates a borrow out when it needs to borrow from the next digit. Since we are subtracting $Y$ and $B_{\text{in}}$ from $X$, a borrow out needs to be generated when $X<Y+B_{\text{in}}$. When a borrow out is generated, 2 is added in the current digit. (This is similar to the subtraction algorithm in decimal. Instead of adding 2, we add 10 when we borrow.) Therefore, $D=X-Y-B_{\text{in}}+2B_{\text{out}}$.

The truth table for the full subtractor is:

Inputs			Outputs
X	Y	Bin	D	Bout
0	0	0	0	0
0	0	1	1	1
0	1	0	1	1
0	1	1	0	1
1	0	0	1	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

Therefore the equation is:

$D=X\oplus Y\oplus B_{in}$

$B_{out}={\bar {X}}B_{in}+{\bar {X}}Y+YB_{in}$

See also

• Adder (electronics)
• Carry-lookahead adder
• Carry-save adder
• Adding machine
• Adder-subtractor

References

1. Foundations Of Digital Electronics by Elijah Mwangi
2. Beltran, A.A., Nones, K., Salanguit, R.L., Santos, J.B., Santos, J.M., & Dizon, K.J. (2021). Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique.

External links

• N bit Binary addition or subtraction using single circuit.